Patents by Inventor Avgerinos V. Gelatos

Avgerinos V. Gelatos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250151374
    Abstract: A method of forming an electrical contact in a semiconductor structure includes performing a cavity shaping process on a semiconductor structures having an n-type metal oxide semiconductor (n-MOS) region and/or a p-type MOS (p-MOS) region, the cavity shaping process comprising forming an n-MOS cavity in an exposed surface of the n-MOS region and/or a p-MOS cavity in an exposed surface of the p-MOS region, wherein the cavity shaping process is configured to increase the surface area of the exposed surface of the n-MOS region or the p-MOS region. In some embodiments, the method includes performing a first selective deposition process to form a p-MOS cavity contact, selectively in the p-MOS cavity.
    Type: Application
    Filed: September 17, 2024
    Publication date: May 8, 2025
    Inventors: Nicolas Louis BREIL, Lisa MCGILL, Manoj VELLAIKAL, Bocheng CAO, Pei LIU, Avgerinos V. GELATOS
  • Patent number: 12293902
    Abstract: Methods and apparatus for processing substrates are provided herein. In some embodiments, a process kit for a substrate support includes: an upper edge ring made of quartz and having an upper surface and a lower surface, wherein the upper surface is substantially planar and the lower surface includes a stepped lower surface to define a radially outermost portion and a radially innermost portion of the upper edge ring.
    Type: Grant
    Filed: July 11, 2022
    Date of Patent: May 6, 2025
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Muhannad Mustafa, Muhammad M. Rasheed, Yu Lei, Avgerinos V. Gelatos, Vikash Banthia, Victor H Calderon, Shi Wei Toh, Yung-Hsin Lee, Anindita Sen
  • Publication number: 20250132146
    Abstract: A method of capping a metal layer includes performing a conversion process to reduce a metal oxide layer formed on a top surface of the metal layer and form a metal sulfide layer on the top surface of the metal layer, exposing the top surface of the metal layer to an oxidizing environment, and performing a removal process to remove the metal sulfide layer.
    Type: Application
    Filed: October 23, 2023
    Publication date: April 24, 2025
    Inventors: Mohammad Mahdi TAVAKOLI, Chandan DAS, Bencherki MEBARKI, Joung Joo LEE, Jiecong TANG, Avgerinos V. GELATOS
  • Patent number: 12281387
    Abstract: Organometallic precursors and methods of depositing high purity metal films are discussed. Some embodiments utilize a method comprising exposing a substrate surface to an organometallic precursor comprising one or more of molybdenum (Mo), tungsten (W), osmium (Os), technetium (Tc), manganese (Mn), rhenium (Re) or ruthenium (Ru), and an iodine-containing reactant comprising a species having a formula RIx, where R is one or more of a C1-C10 alkyl, C3-C10 cycloalkyl, C2-C10 alkenyl, or C2-C10 alkynyl group, I is an iodine group and x is in a range of 1 to 4 to form a carbon-less iodine-containing metal film. Some embodiments advantageously provide methods of forming metal films having low carbon content (e.g., having greater than or equal to 95% metal species on an atomic basis), without using an oxidizing agent or a reductant.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: April 22, 2025
    Assignee: Applied Materials, Inc.
    Inventors: Feng Q. Liu, Mark Saly, David Thompson, Annamalai Lakshmanan, Avgerinos V. Gelatos, Joung Joo Lee
  • Publication number: 20250125157
    Abstract: The methods of the present disclosure enable formation of highly conductive contacts that facilitate in increasing the device speed and lowering the operating voltages of semiconductor devices such as, but not limited to, metal-on-semiconductor (MOS) transistors and the like. In one embodiment, the methods create the optimal contacts, useful in N type or P type MOS devices, by forming metal-insulator-semiconductor (MIS) contact structure or a non-stoichiometric layer contact structure. It is noted that N type or P type contacts require different work function metals to achieve a low Schottky barrier height (SBH).
    Type: Application
    Filed: April 12, 2024
    Publication date: April 17, 2025
    Inventors: Michael HAVERTY, Avgerinos V. GELATOS, Gaurav THAREJA, Lauren Mary BAGBY, Lakmal C. KALUTARAGE, Jeffrey W. ANTHIS, Archana KUMAR
  • Publication number: 20250081569
    Abstract: A method of forming an electrical contact in a semiconductor structure includes performing a cavity shaping process on a semiconductor structure having a p-type semiconductor region for a p-type metal oxide semiconductor (p-MOS) device, the cavity shaping process comprising forming a first cavity in an exposed surface of the p-type semiconductor region, performing a first selective deposition process to form a first cavity contact, selectively in the first cavity, and performing a metal treatment process on the formed first cavity contact, to remove oxides at interfaces of the first cavity contact with the first cavity.
    Type: Application
    Filed: August 28, 2024
    Publication date: March 6, 2025
    Inventors: Nicolas Louis BREIL, Avgerinos V. GELATOS
  • Publication number: 20240404888
    Abstract: Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor. The substrate may be pre-cleaned. A ruthenium silicide (RuSi) layer is selectively deposited on the p transistor. A titanium silicide (TiSi) layer is formed on the n transistor and the p transistor. An optional barrier layer may be formed on the titanium silicide (TiSi) layer. The method may be performed in a processing chamber without breaking vacuum.
    Type: Application
    Filed: August 7, 2024
    Publication date: December 5, 2024
    Applicant: Applied Materuals, Inc.
    Inventors: Thomas Anthony Empante, Avgerinos V. Gelatos, Zhibo Yuan, Liqi Wu, Joung Joo Lee, Byunghoon Yoon
  • Publication number: 20240360549
    Abstract: A method includes performing a reactant step of a deposition cycle of a deposition process to form a molybdenum (Mo)-based material, performing a Mo precursor step of the deposition cycle, and performing a treatment step of the deposition cycle. Performing the reactant step includes introducing a reactant, performing the Mo precursor step includes introducing a Mo precursor, and performing the treatment step includes introducing a treatment gas. The deposition process is performed at a temperature that is less than or equal to about 450° C.
    Type: Application
    Filed: April 27, 2023
    Publication date: October 31, 2024
    Inventors: Feng Q. Liu, Byunghoon Yoon, Joung-Joo Lee, Avgerinos V. Gelatos, Mark J. Saly
  • Publication number: 20240331999
    Abstract: Exemplary semiconductor processing methods may include providing a substrate to a processing region of a semiconductor processing chamber. The substrate may include an alternating stack of materials. A feature may extend through the alternating stack of materials. One material of the alternating stack of materials may include a silicon-containing material. A native oxide material may be disposed on at least a portion of exposed surfaces of the silicon-containing material. The methods may include performing a pre-clean treatment on the substrate. The methods may include providing a fluorine-containing precursor to the processing region. The methods may include contacting the substrate with the fluorine-containing precursor, wherein the contacting removes native oxide from the silicon-containing material.
    Type: Application
    Filed: February 15, 2024
    Publication date: October 3, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Ying-Bing Jiang, Avgerinos V. Gelatos, Joung Joo Lee, Bencherki Mebarki, Xianmin Tang, In Seok Hwang, Zhijun Chen
  • Publication number: 20240332023
    Abstract: The present disclosure relates to a method of selectively forming a silicide in high-aspect ratio structures by use of a multistep deposition process. A first precursor gas is delivered to a surface disposed within a processing region of a process chamber maintained at a first process pressure, where the substrate is maintained at a first temperature for a first period of time. A purge gas is delivered to for a second period of time after the first period of time has elapsed. A second precursor gas is delivered to the surface of the substrate. The second precursor being maintained at a second process pressure while the substrate is maintained at a second temperature for a third period of time. The purge gas is delivered to the processing region for a fourth period of time after the third period of time has elapsed.
    Type: Application
    Filed: March 29, 2024
    Publication date: October 3, 2024
    Inventors: Ying-Bing JIANG, In Seok HWANG, Zhijun CHEN, Avgerinos V. GELATOS, Joung Joo LEE, Xianmin TANG, Fredrick FISHBURN, Le ZHANG, Wangee KIM, Mahendra PAKALA
  • Publication number: 20240327991
    Abstract: Embodiments herein describe a method of manufacturing an interconnect structure. The method includes depositing a selective tungsten layer on a tungsten containing surface, the tungsten containing surface is disposed within a feature, wherein the feature includes one or more surfaces that comprise a dielectric material, and the depositing of the selective tungsten layer results in a residue forming on the dielectric material. The method also includes performing a reducing reaction via exposing the residue and dielectric material to an organosilane containing precursor soak, wherein the organosilane containing precursor reduces the residue. The method further includes forming a conformal layer over the dielectric material and the selective tungsten layer.
    Type: Application
    Filed: December 29, 2023
    Publication date: October 3, 2024
    Inventors: Mohammad Mahdi TAVAKOLI, Avgerinos V. GELATOS, Joung Joo LEE
  • Publication number: 20240313079
    Abstract: The present technology includes semiconductor devices and methods with improved contact resistivity. Semiconductor devices include a substrate base, a silicon oxide disposed on the base defining one or more features, a bi-metallic silicide layer disposed on the substrate in the one or more features, and at least a first metal layer. The bi-metallic silicide layer includes a first metal, a second metal different than the first metal, and a silicon containing compound, and includes greater than or about 0.8 E+14 per cm?2 second metal atoms. The first metal layer includes the first metal and overlies the bi-metallic silicide layer.
    Type: Application
    Filed: March 16, 2023
    Publication date: September 19, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Sefa Dag, El Mehdi Bazizi, Gaurav Thareja, Avgerinos V. Gelatos, Gang Shen
  • Patent number: 12094785
    Abstract: Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor. The substrate may be pre-cleaned. A ruthenium silicide (RuSi) layer is selectively deposited on the p transistor. A titanium silicide (TiSi) layer is formed on the n transistor and the p transistor. An optional barrier layer may be formed on the titanium silicide (TiSi) layer. The method may be performed in a processing chamber without breaking vacuum.
    Type: Grant
    Filed: December 15, 2021
    Date of Patent: September 17, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Thomas Anthony Empante, Avgerinos V. Gelatos, Zhibo Yuan, Liqi Wu, Joung Joo Lee, Byunghoon Yoon
  • Publication number: 20240234209
    Abstract: Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor. The substrate is pre-cleaned. A molybdenum silicide (MoSi) layer is deposited on one or more of the p transistor and the n transistor. A titanium silicide (TiSi) layer is formed on the n transistor and the p transistor. A capping layer may be formed on the titanium silicide (TiSi) layer. The method may be an integrated method performed in a processing chamber without breaking vacuum.
    Type: Application
    Filed: December 19, 2023
    Publication date: July 11, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Avgerinos V. Gelatos, Yang Hu, Thomas Anthony Empante, Gaurav Thareja, Joung Joo Lee, Shi You, Pranav Ramesh, Chi H. Ching, Nicolas Breil
  • Publication number: 20240203741
    Abstract: A method of forming an electrical contact in a semiconductor structure includes performing a cavity shaping process on a semiconductor structures having an n-type metal oxide semiconductor (n-MOS) region and a p-type MOS (p-MOS) region, the cavity shaping process comprising forming an n-MOS cavity in an exposed surface of the n-MOS region and a p-MOS cavity in an exposed surface of the p-MOS region, and performing a first selective deposition process to form a p-MOS cavity contact, selectively in the p-MOS cavity.
    Type: Application
    Filed: November 8, 2023
    Publication date: June 20, 2024
    Inventors: Nicolas Louis BREIL, Avgerinos V. GELATOS
  • Publication number: 20240194605
    Abstract: A semiconductor structure includes a first level comprising a metal layer within a first dielectric layer formed on a substrate, a second level formed on the first level, the second level comprising an interconnect within a second dielectric layer and a barrier layer formed around the interconnect, and a metal capping layer disposed at an interface between the metal layer and the interconnect, wherein the metal capping layer comprises tungsten (W) and has a thickness of between 20 ? and 40 ?.
    Type: Application
    Filed: December 8, 2023
    Publication date: June 13, 2024
    Inventors: Mohammad Mahdi TAVAKOLI, Avgerinos V. GELATOS, Jiajie CEN, Kevin KASHEFI, Joung Joo LEE, Zhihui LIU, Yang ZHOU, Zhiyuan WU, Meng-Shan WU
  • Publication number: 20240191354
    Abstract: Methods of depositing a metal silicide on a substrate are provided herein. In some embodiments, a method of depositing a metal silicide on a substrate having a silicon containing surface includes: creating a plasma comprising a first gas in a plasma region in a chemical vapor deposition (CVD) chamber, wherein the plasma region is disposed between a lid heater and a showerhead; flowing the first gas through a plurality of first openings of the showerhead to an activation region in the CVD chamber disposed between the showerhead and the substrate; flowing a second gas comprising a metal precursor in a non-plasma state through a plurality of second openings of the showerhead to the activation region, wherein the plurality of second openings are fluidly independent from the plurality of first openings within the showerhead; mixing the first gas with the second gas to activate the second gas in the activation region; and exposing the silicon containing surface of the substrate to the activated second gas.
    Type: Application
    Filed: December 9, 2022
    Publication date: June 13, 2024
    Inventors: Ying-Bing JIANG, Joung Joo LEE, Xianmin TANG, Jiang LU, Avgerinos V. GELATOS, Dien-yeh WU, Weifeng YE, Yiyang WAN, Gary HOW, Joseph HERNANDEZ
  • Publication number: 20240079241
    Abstract: Methods for forming a semiconductor structure and semiconductor structures are described. Some embodiments of the method comprise patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor. The substrate is pre-cleaned. A molybdenum film is selectively deposited on the p transistor.
    Type: Application
    Filed: August 25, 2023
    Publication date: March 7, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Thomas Anthony Empante, Avgerinos V. Gelatos
  • Publication number: 20240052480
    Abstract: Methods and apparatus for selectively depositing a molybdenum layer on a substrate which includes contacting a substrate surface initially comprising a first portion comprising amorphous silicon, and a second portion comprising silicon and germanium with a molybdenum precursor to selectively form a molybdenum layer on the second portion of the substrate surface.
    Type: Application
    Filed: August 8, 2023
    Publication date: February 15, 2024
    Inventors: Avgerinos V. GELATOS, Thomas EMPANTE, Yang HU
  • Publication number: 20240038859
    Abstract: A contact stack of a semiconductor device comprises: a source/drain region; a metal silicide layer above the source/drain region; a metal cap layer directly on the metal silicide layer; and a conductor on the metal cap layer. A method comprises: depositing a metal silicide layer in a feature of a substrate; in the absence of an air break after the depositing of the metal silicide layer, preparing a metal cap layer directly on the metal silicide layer; and depositing a conductor on the metal cap layer.
    Type: Application
    Filed: October 12, 2023
    Publication date: February 1, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Bencherki Mebarki, Joung Joo Lee, Wenting Hou, Takashi Kuratomi, Avgerinos V. Gelatos, Jianxin Lei, Liqi Wu, Raymond Hoiman Hung, Tae Hong Ha, Xianmin Tang