Abstract: A multi-level clock signal distribution network comprises a plurality of lower network levels comprising at least a first lower network level and a lowermost network level that is connected to one or more lowermost clock signal driving circuits connectable to receive a clock signal; and a topmost network level arranged to distribute the clock signal to a plurality of clocked circuits, and connected to a plurality of topmost clock signal driving circuits connected to receive the clock signal from the first lower network level. The lowermost network level comprises at least one net and each of the plurality of lower network levels except the lowermost network level comprises a plurality of nets and is connected to a corresponding plurality of lower clock signal driving circuits being connected to receive the clock signal from a subjacent one of the plurality of lower network levels, wherein each of the plurality of nets is driven by all nets of the subjacent one.

Abstract: A multi-level clock signal distribution network comprises a plurality of lower network levels comprising at least a first lower network level and a lowermost network level that is connected to one or more lowermost clock signal driving circuits connectable to receive a clock signal; and a topmost network level arranged to distribute the clock signal to a plurality of clocked circuits, and connected to a plurality of topmost clock signal driving circuits connected to receive the clock signal from the first lower network level. The lowermost network level comprises at least one net and each of the plurality of lower network levels except the lowermost network level comprises a plurality of nets and is connected to a corresponding plurality of lower clock signal driving circuits being connected to receive the clock signal from a subjacent one of the plurality of lower network levels, wherein each of the plurality of nets is driven by all nets of the subjacent one.

Abstract: An integrated circuit, including: (i) a power gated circuit which power supply is shut down during a low-power period; (ii) a retention circuit, coupled to the power gated circuit during at least a portion of a non-low-power period, the retention circuit is adapted to store, during the low-power period, state information reflecting a state of the power gated circuit before the low-power period started; (iii) a first portion of the power grid, coupled to the retention circuit and to a first end of a power supply switch, adapted to provide to the retention circuit a supply voltage during the low-power period and during a non-low-power period; wherein the power supply switch is open during the low-power period and is closed during the non-low-power period; and (iv) a second portion of the power grid, coupled to a second end of the power supply switch and to the power gated circuit; adapted to supply a gated supply voltage to the power gated circuit during the non-low-power period.

Abstract: An integrated circuit, including: (i) a power gated circuit which power supply is shut down during a low-power period; (ii) a retention circuit, coupled to the power gated circuit during at least a portion of a non-low-power period, the retention circuit is adapted to store, during the low-power period, state information reflecting a state of the power gated circuit before the low-power period started; (iii) a first portion of the power grid, coupled to the retention circuit and to a first end of a power supply switch, adapted to provide to the retention circuit a supply voltage during the low-power period and during a non-low-power period; wherein the power supply switch is open during the low-power period and is closed during the non-low-power period; and (iv) a second portion of the power grid, coupled to a second end of the power supply switch and to the power gated circuit; adapted to supply a gated supply voltage to the power gated circuit during the non-low-power period.