Patents by Inventor Axel Christoph Brintzinger
Axel Christoph Brintzinger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7087975Abstract: A semiconductor device is provided which is formed of a wafer having on a surface thereof an area efficient arrangement of at least two antifuses in vertically stacked relation and sharing a common intermediate electrode therebetween. The arrangement includes at least one lower antifuse having a lower counter electrode and a lower fusible insulator portion defining a lower fuse element of an initial high electrical resistance state which interconnects the lower counter electrode with the common intermediate electrode, and at least one upper antifuse, which may be the same as or different from the lower antifuse, the upper antifuse having an upper counter electrode and an upper fusible insulator portion defining an upper fuse element of an initial high electrical resistance state which interconnects the upper counter electrode with the common intermediate electrode.Type: GrantFiled: December 28, 2000Date of Patent: August 8, 2006Assignee: Infineon Technologies AGInventors: Gunther Lehmann, Axel Christoph Brintzinger, Gabriel Daniel
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Publication number: 20040217441Abstract: A semiconductor device is provided which is formed of a wafer having on a surface thereof an area efficient arrangement of at least two antifuses in vertically stacked relation and sharing a common intermediate electrode therebetween. The arrangement includes at least one lower antifuse having a lower counter electrode and a lower fusible insulator portion defining a lower fuse element of an initial high electrical resistance state which interconnects the lower counter electrode with the common intermediate electrode, and at least one upper antifuse, which may be the same as or different from the lower antifuse, the upper antifuse having an upper counter electrode and an upper fusible insulator portion defining an upper fuse element of an initial high electrical resistance state which interconnects the upper counter electrode with the common intermediate electrode.Type: ApplicationFiled: December 28, 2000Publication date: November 4, 2004Inventors: Gunther Lehmann, Axel Christoph Brintzinger, Gabriel Daniel
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Patent number: 6720212Abstract: Disclosed is a method of ball grid array packaging, comprising the steps of providing a semiconductor die having a metal conductors thereon, covering said metal conductors with an insulative layer, etching through said insulative layer so as to provide one or more openings to said metal conductors, depositing a compliant material layer, etching through said compliant material layer so as to provide one or more openings to said metal conductors, depositing a substantially homogenous conductive layer, patterning said conductive layer so as to bring at least one of said metal conductors in electrical contact with one or more pads, each said pad comprising a portion of said conductive layer disposed upon said compliant material, and providing solder balls disposed upon said pads. Also disclosed is the apparatus made from the method.Type: GrantFiled: March 14, 2002Date of Patent: April 13, 2004Assignee: Infineon Technologies AGInventors: Werner Robl, Thomas Goebel, Axel Christoph Brintzinger, Gerald Friese
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Publication number: 20030183913Abstract: Disclosed is a method of ball grid array packaging, comprising the steps of providing a semiconductor die having a metal conductors thereon, covering said metal conductors with an insulative layer, etching through said insulative layer so as to provide one or more openings to said metal conductors, depositing a compliant material layer, etching through said compliant material layer so as to provide one or more openings to said metal conductors, depositing a substantially homogenous conductive layer, patterning said conductive layer so as to bring at least one of said metal conductors in electrical contact with one or more pads, each said pad comprising a portion of said conductive layer disposed upon said compliant material, and providing solder balls disposed upon said pads. Also disclosed is the apparatus made from the method.Type: ApplicationFiled: March 14, 2002Publication date: October 2, 2003Applicant: Infineon Technologies North America Corp.Inventors: Werner Robl, Thomas Goebel, Axel Christoph Brintzinger, Gerald Friese
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Patent number: 6495918Abstract: A semiconductor chip, in accordance with the present invention, includes a substrate and a crack stop structure. The crack structure includes a first conductive line disposed over the substrate and at least two first contacts connected to the substrate and to the first conductive line. The at least two first contacts are spaced apart from each other and extend longitudinally along a length of the first conductive line. A second conductive line is disposed over a portion of the first conductive line, and at least two second contacts are connected to the first conductive line and the second conductive line. The at least two second contacts are spaced apart from each other and extend longitudinally along a length of the second conductive line.Type: GrantFiled: September 5, 2000Date of Patent: December 17, 2002Assignees: Infineon Technologies AG, International Business Machines CorporationInventor: Axel Christoph Brintzinger
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Patent number: 6495901Abstract: A semiconductor device has a first conductor and a second conductor for fuse terminals. A fuse portion is disposed on a different level relative to both the first conductor and the second conductor. A first contact connects the fuse portion to the first conductor, and a second contact connects the fuse portion to the second conductor.Type: GrantFiled: January 30, 2001Date of Patent: December 17, 2002Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Axel Christoph Brintzinger, Chandrasekhar Narayan, David Lachtrupp, Kenneth Arndt
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Publication number: 20020100956Abstract: A semiconductor device has a first conductor and a second conductor for fuse terminals. A fuse portion is disposed on a different level relative to both the first conductor and the second conductor. A first contact connects the fuse portion to the first conductor, and a second contact connects the fuse portion to the second conductor.Type: ApplicationFiled: January 30, 2001Publication date: August 1, 2002Inventors: Axel Christoph Brintzinger, Chandrasekhar Narayan, David Lachtrupp, Kenneth Arndt
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Patent number: 6242789Abstract: A fuse for semiconductor devices in accordance with the present invention includes a substrate having a conductive path disposed on a surface thereof, a dielectric layer disposed on the substrate and a vertical fuse disposed perpendicularly to the surface through the dielectric layer and connecting to the conductive path, the vertical fuse forming a cavity having a liner material disposed along vertical surfaces of the cavity, the vertical surfaces being melted to blow the fuse. Methods for fabrication of the vertical fuse are also included.Type: GrantFiled: February 23, 1999Date of Patent: June 5, 2001Assignees: Infineon Technologies North America Corp., International Business Machines CorporationInventors: Stefan J. Weber, Axel Christoph Brintzinger, Roy Iggulden, Mark Hoinkis, Chandrasekhar Narayan, Robert Van Den Berg
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Patent number: 6218279Abstract: A fuse for semiconductor devices in accordance with the present invention includes a substrate having a conductive path disposed on a surface thereof, a dielectric layer disposed on the substrate and a vertical fuse disposed perpendicularly to the surface through the dielectric layer and connecting to the conductive path, the vertical fuse forming a cavity having a liner material disposed along vertical surfaces of the cavity, the vertical surfaces being melted to blow the fuse. Methods for fabrication of the vertical fuse are also included.Type: GrantFiled: February 24, 2000Date of Patent: April 17, 2001Assignees: Infineon Technologies North America Corp., International Business Machines CorporationInventors: Stefan J. Weber, Axel Christoph Brintzinger, Roy Iggulden, Mark Hoinkis, Chandrasekhar Narayan, Robert Van den Berg
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Patent number: 6060398Abstract: A method and apparatus for protecting a neighboring area that is adjacent to a first area that is to be etched. The method includes creating a guard cell substantially surrounding the first area, but excluding the neighboring area. The guard cell is formed of a material that is substantially selective to the etch process subsequently employed to etch within the first area. After the guard cell is formed, an etch is performed within the first area, while the guard cell prevents etching of the neighboring are outside the guard cell.Type: GrantFiled: March 9, 1998Date of Patent: May 9, 2000Assignee: Siemens AktiengesellschaftInventors: Axel Christoph Brintzinger, Ravikumar Ramachandran, Senthil Kumar Srinivasan