Abstract: An apparatus includes an output pad, a plurality of arrays of test devices, a hierarchy of selection devices, and address logic. The hierarchy of selection devices includes a plurality of levels coupled between the output pad and the arrays of test devices. Each test device is coupled to a selection device in a first level of the hierarchy, and the selection devices for each array are coupled to one selection device in a second level of the hierarchy. The address logic is coupled to the hierarchy of selection devices and operable to enable one selection device in each level of the hierarchy to couple a selected test device in a selected array to the output pad.

Abstract: An integrated circuit device can include a number of test structures, whereby each test structure includes a TSV and a plurality of devices-under-test (DUTs). Each of the DUTs in a test structure has a different positional relationship, such as proximity or orientation, to the TSV. A test system can measure selected parameters such as transistor threshold voltage, leakage current, or other parameters, for each of the DUTs in the test structure. The measurements for different test structures can be combined to characterize nominal values of the measured parameter and its statistical distribution. This information provides an indication of how the measured parameter varies according to the positional relationship of a TSV to a DUT.

Abstract: Methods for fabricating a hybrid interconnect structure that possesses a higher interconnect capacitance in one set of regions than in other regions on the same microelectronic chip. Several methods to fabricate such a structure are provided. Circuit implementations of such hybrid interconnect structures are described that enable increased static noise margin and reduce the leakage in SRAM cells and common power supply voltages for SRAM and logic in such a chip. Methods that enable combining these circuit benefits with higher interconnect performance speed and superior mechanical robustness in such chips are also taught.

Abstract: Methods for fabricating a hybrid interconnect structure that possesses a higher interconnect capacitance in one set of regions than in other regions on the same microelectronic chip. Several methods to fabricate such a structure are provided. Circuit implementations of such hybrid interconnect structures are described that enable increased static noise margin and reduce the leakage in SRAM cells and common power supply voltages for SRAM and logic in such a chip. Methods that enable combining these circuit benefits with higher interconnect performance speed and superior mechanical robustness in such chips are also taught.

Abstract: Circuits and methods are provided to implement low voltage, higher performance semiconductor memory devices such as CMOS static random access memory (SRAM) or multi-port register files. For example, circuits and methods are provided for dynamically adjusting power supply and/or ground line voltages that are applied to the memory cells during different modes of memory operation to enable low voltage, high performance operation of the memory devices.

Abstract: A power gate structure and corresponding method are provided for controlling the ground connection of a logic circuit for a plurality of modes, where the power gate structure includes an NFET transistor, a PFET transistor in signal communication with the NFET transistor, source to source and drain to drain, respectively, a ground node in signal communication with the drains of the transistors, and a ground rail in signal communication with the sources of the transistors; and the corresponding method includes decoupling the logic circuit from the ground connection in a first or active mode, holding the logic circuit at about a threshold voltage above the ground connection in a second or state retention mode, and cutting off the current flow between the logic circuit and the ground connection in a third or non-state retentive mode.

Abstract: A method for minimum metal consumption power distribution includes the steps of forming a circuit having a plurality of circuit components on an electrically insulated substrate and forming a plurality of supply voltage regulators on the electrically insulating substrate wherein each of the plurality of supply voltage regulators is located adjacent to each of the plurality of circuit components respectively, and each of the plurality of supply voltage regulators is connected to each of the plurality of circuit components respectively for generating a regulated voltage rail output to each of the plurality of circuit components respectively.

Abstract: A memory device has a memory cell including a plurality of active devices, which can be switched on by an applied threshold voltage. A power line is coupled to at least one storage node by one of the active devices. One other of the active devices couples a virtual ground to the storage node. Potentials of the power line and the virtual ground cause the plurality of active devices to be selectively operated in near subthreshold and/or superthreshold regimes in accordance with a mode of operation.

Abstract: A power gate structure and corresponding method are provided for controlling the ground connection of a logic circuit for a plurality of modes, where the power gate structure includes an NFET transistor, a PFET transistor in signal communication with the NFET transistor, source to source and drain to drain, respectively, a ground node in signal communication with the drains of the transistors, and a ground rail in signal communication with the sources of the transistors; and the corresponding method includes decoupling the logic circuit from the ground connection in a first or active mode, holding the logic circuit at about a threshold voltage above the ground connection in a second or state retention mode, and cutting off the current flow between the logic circuit and the ground connection in a third or non-state retentive mode.

Abstract: A memory cell includes at least one active device for selectively connecting a supply voltage node to a power line. The power line couples capacitive elements through the at least one active device to the supply voltage node to maintain a high state while accessing a storage node. The high state is provided by a boost created by the addition of the capacitive elements.

Abstract: A read and write assist and restore circuit for a memory device includes a first device, which is responsive to a potential on a bit line such that the potential on the bit line activates the first device. A second device is driven by the first device such that when the first device is activated, a change in the bit line potential is reinforced with positive feedback by the second device during a wordline active period to enable write-back of data lost as a result of threshold voltage fluctuations in memory cell transistors coupled to the bit line.

Abstract: An SRAM system is provided having an array of SRAM cells including at least one circuit receiving a first power voltage and a power control circuit for supplying a second power voltage to at least one selected circuit of the at least one circuit. The system is one of a memory array and a logic system, and a circuit of the at least one circuit is one of a memory cell of the memory array, a sense amplifier of the memory array and a path of the logic system. A method is also provided for providing a power supply voltage to at least one circuit of a system.

Abstract: An SRAM system is provided having an array of SRAM cells receiving a first power voltage. The SRAM system includes at least one circuit receiving a first power voltage, and a power control circuit for supplying a second power voltage to at least one selected circuit of the at least one circuit of the system. The system is one of a memory array and a logic system, and a circuit of the at least one circuit is one of a memory cell of the memory array, a sense amplifier of the memory array and a path of the logic system. Furthermore, a method is provided for providing a power supply voltage to at least one circuit of a system. The method includes the steps of providing a first power supply voltage to the at least one circuit of the system, and providing a second power supply voltage to at least one selected circuit of the at least one circuit.

Abstract: A source pulsed, dynamic threshold complementary metal oxide semiconductor static random access memory dynamically controls cell transistor threshold voltage to increase cell stability, decrease cell standby power, and reduce cell delay. A memory cell includes a low storage node and a high storage node wherein the low storage node is driven below Vss during a read access and the high storage node is driven above Vdd during the read access.

Abstract: A source pulsed complementary metal oxide semiconductor static random access memory offers higher cell stability, lower bit line delay, and lower standby power than previously available in low-voltage devices. A memory cell includes a first pull-up device, a first pull-down device connected to the first pull-up device, a first cell access device connected to the first pull-down device, a second pull-up device connected to the first pull-up device, a second pull-down device connected to the second pull-up device, and a second cell access device connected to the second pull-down device wherein the first cell access device and the second cell access device each have a gate connected to a word line that is driven to a voltage less than Vss except during cell access and is pulsed to Vdd during cell access.