Abstract: Various shapes of microstructures and patterns of microstructures are provided to reduce the visibility of fingerprints, or other foreign marks, that occur on the surface of substrates due to handling. The microstructures may be formed directly on an exterior surface of a substrate to render the substrate fingerprint resistant, or formed on a surface of a polymeric sheet to provide a fingerprint-resistant protective layer that may be disposed onto a surface of a substrate (e.g., an optical display). The size, shape, orientation, and distribution of the microstructures across the surface of the substrate, or protective layer, may be optimized to enhance the durability of the microstructures and/or to impart a diffusing surface to the substrate for the particular application of the substrate.

Abstract: Enhancement of the contrast ratio of optical flat panel displays by integrating an array of corner-cube retroreflectors into the front face of the optical display, said integration involving mutual adaptation of both the display and the corner-cube retroreflector geometry to unite the two disparate optical systems. The light emission from the display passes through the truncated vertex of the corner-cubes to the observer. The display directs its emitted light through the vertex apertures (either as a natural behavior, or by interposing a registered array of light concentrators between the display and the corner-cube array). The improvement in contrast ratio arises due to the corner-cube retroreflectors' ability to direct incident ambient light directly back to its source, rather than the viewer's eyes. Ambient light reflections are not attenuated but maximized; this maximization is directed away from the viewer, causing the array to appear dark even in direct sunlight.

Abstract: An electronic device has a plurality of selectable capabilities. The capabilities may include CPU speed, NIC speed, various protocols, or, in general, any parameters, characteristics or features which a user might desire to have in the electronic device. The device receives a key, such as from an external licensing authority, and the key specifies which capabilities the device should use to configure itself. The user may have to pay the licensing authority for the key. The electronic device thus can be configured into any one of a plurality of capabilities without having to change any hardware—the user simply purchases a key commensurate with a capability desired by the user.

Abstract: Apparatus and method are disclosed for down scaling performance of a multibus multiprocessor computer system. One or more busses associated with one or more failed processors or devices are disabled to allow operation from remaining busses. If errors or power failure are detected in a processor or bus device the computer system may reboot and, using the apparatus and method of the present invention, the bus associated with the defective processors or devices may be disabled upon reboot. The one or more affected busses may be disabled and the computer system may be brought back up in a single-bus operational mode or a multiple bus operational mode where an alternate bus is designated as the boot bus.

Abstract: Apparatus and method are disclosed for down scaling performance of a multibus multiprocessor computer system. One or more busses associated with one or more failed processors or devices are disabled to allow operation from remaining busses. If errors or power failure are detected in a processor or bus device the computer system may reboot and, using the apparatus and method of the present invention, the bus associated with the defective processors or devices may be disabled upon reboot. The one or more affected busses may be disabled and the computer system may be brought back up in a single-bus operational mode or a multiple bus operational mode where an alternate bus is designated as the boot bus.

Abstract: Apparatus and method are disclosed for down scaling performance of a multibus multiprocessor computer system. One or more busses associated with one or more failed processors or devices are disabled to allow operation from remaining busses. If errors or power failure are detected in a processor or bus device the computer system may reboot and, using the apparatus and method of the present invention, the bus associated with the defective processors or devices may be disabled upon reboot. The one or more affected busses may be disabled and the computer system may be brought back up in a single-bus operational mode or a multiple bus operational mode where an alternate bus is designated as the boot bus.

Abstract: A computer system having a system ROM comprising a flash or bulk EPROM replacing a block flash or boot block EPROM, and a second ROM to store the primary boot code. In a first embodiment, a single block EPROM is replaced with a bulk EPROM and a ROM, where the ROM is preferably a one-time programmable ROM. The primary boot code is copied into the ROM thereby preventing its erasure. The bulk EPROM is reprogrammed if desired. Separate decode logic detects an address to the primary boot code and enables the ROM. In a second system using a block EPROM and a bulk EPROM as the system ROM, the block EPROM is replaced with a bulk EPROM, and the primary boot code is copied into both bulk EPROMs, preferably at mirrored locations. An external switch is provided with appropriate logic, so that the user may select between either of the bulk EPROMs to boot the system. Thus, if the system is unable to boot from one of the bulk EPROMs, the user may flip the switch to access the primary boot code from the other bulk EPROM.

Abstract: A method and apparatus for enabling a computer user to implement intelligent input/output processing involves a connector adapted to receive interrupt request signals from input/output devices in a plurality of slots contained on an input/output bus. When an intelligent input/output card is inserted into the connector, the card can process certain of the interrupt requests from devices contained in slots connected to the input/output bus. This augments the processing of input/output device interrupt requests without burdening the host processor. Thus, a computer system arranged in a peer architecture may be subsequently enhanced with a intelligent input/output card, without burdening all purchasers with the cost of expensive hardware to enable the subsequent upgrade.

Abstract: An electronic component chassis with a first side, a second side, and having a preferred airflow therebetween. The first side of the electronic component chassis includes an insertion slot for receiving a removable component that is to be inserted into the electronic component chassis. The insertion slot is automatically closed by an airflow control door when the removable component is not housed by the electronic component chassis. By closing the insertion slot, the preferred airflow between the first side and the second side is enabled.

Abstract: A modular computer chassis configurable for both rack mounting and free standing use includes a housing with a multiple compartments for receiving computer devices and peripherals therein. The housing further includes side access panels and a top access panel, each being attachable and removable from the frame of the chassis without tools. The frame of the modular computer chassis is configured with slots to receive corresponding tabs on each of the side and top panels which facilitate the quick installation and removal of the side and top panels from the frame of the chassis. Multiple tool-less fasteners are used to further secure side and top covers to the frame of the chassis.

Abstract: A computer system has a central processing unit and a bus. A first bus device and a second bus device are connected to the bus. A circuit is connected to configure the second bus device to be addressable by the central processing unit via the bus only by interaction with the first bus device. The first bus device may be an I.sub.2 O processor, and the second bus device may be an I.sub.2 O subordinate bus device.

Abstract: Control is switched from a first server to a second server in a fault tolerant system. The first and second servers are coupled with an expansion bus in an expansion box for communication with the expansion bus. An indication is provided to the second server to indicate the activity state of the first server. Communication between the first server and the expansion box is disabled if the indication indicates the first server is inactive. Communication between the second server and the expansion bus is disabled if the indication indicates that the first server is active. Communication between the second server is enabled if the indication indicates that the first server is inactive. The indication includes a heartbeat message transmitted periodically to the second server. The expansion bus includes a PCI bus.

Abstract: A power supply circuit is provided for a battery powered real time clock in a microprocessor based computer system. The power supply circuit monitors the output of the original battery and provides a warning indication when the battery output begins to drift or fade. A replacement battery may then be connected to the circuit. The circuit then substitutes power from the replacement battery for that from the original battery.