Patents by Inventor Babette van Antwerpen
Babette van Antwerpen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220277123Abstract: A method is provided for using an integrated circuit design tool to optimize a circuit design for an integrated circuit. Optimizations that affect first circuits in the circuit design and that are performed during synthesis of the circuit design for the integrated circuit are recorded in first records in a database. Second records are recorded in the database that indicate second circuits in the circuit design that fanin to or fanout from the first circuits and that are affected by the optimizations. A root cause of at least one of the optimizations is determined using the first and the second records in the database. A sequence of the optimizations affecting the first and the second circuits is determined using the first and the second records in the database.Type: ApplicationFiled: May 17, 2022Publication date: September 1, 2022Applicant: Intel CorporationInventors: Babette Van Antwerpen, Mindy Lam
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Patent number: 9230047Abstract: A method for designing a system on a target device is disclosed. A partition in the system with a plurality of instances from an extraction netlist is identified. Synthesis optimizations are performed on the partition to generate a synthesis optimization solution. The synthesis optimization solution is applied to the plurality of instances in the system.Type: GrantFiled: June 11, 2010Date of Patent: January 5, 2016Assignee: Altera CorporationInventors: Babette Van Antwerpen, Gregg William Baeckler
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Patent number: 9053274Abstract: An electronic automation system performs register retiming on a logic design, which may be a logic design for a programmable logic integrated circuit. Register retiming is a moving or rearranging of registers across combinatorial logic in a design in order to improve a maximum operating frequency or fmax. In one implementation, the system includes machine-readable code, which may be stored on a computer-readable medium such as a disk, executing on a computer. The system balances timing in order to trade off delays between critical and noncritical paths. Register retiming may make changes to a design at a gate level.Type: GrantFiled: July 2, 2014Date of Patent: June 9, 2015Assignee: Altera CorporationInventors: Babette van Antwerpen, Michael D. Hutton, Gregg William Baeckler, Jinyong Yuan
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Patent number: 8954906Abstract: A method for designing a system to be implemented on a target device includes performing a first synthesis run on an entire design of a system with a first setting to generate a first cell netlist for the entire design of the system. A second synthesis run is performed on the entire design for the system with a second setting and is performed in parallel with the first synthesis procedure to generate a second cell netlist for the entire design of the system. A merged cell netlist is generated that includes a first section of logic from the first netlist and a second section of logic from the second cell netlist.Type: GrantFiled: January 10, 2014Date of Patent: February 10, 2015Assignee: Altera CorporationInventors: Gregg William Baeckler, Babette Van Antwerpen
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Patent number: 8806399Abstract: An electronic automation system performs register retiming on a logic design, which may be a logic design for a programmable logic integrated circuit. Register retiming is a moving or rearranging of registers across combinatorial logic in a design in order to improve a maximum operating frequency or fmax. In one implementation, the system includes machine-readable code, which may be stored on a computer-readable medium such as a disk, executing on a computer. The system balances timing in order to trade off delays between critical and noncritical paths. Register retiming may make changes to a design at a gate level.Type: GrantFiled: March 13, 2013Date of Patent: August 12, 2014Assignee: Altera CorporationInventors: Babette van Antwerpen, Michael D. Hutton, Gregg William Baeckler, Jinyong Yuan
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Patent number: 8661380Abstract: A method for designing a system to be implemented on a target device includes performing a first synthesis run on an entire design of a system with a first setting to generate a first cell netlist for the entire design of the system. A second synthesis run is performed on the entire design for the system with a second setting and is performed in parallel with the first synthesis procedure to generate a second cell netlist for the entire design of the system. A merged cell netlist is generated that includes a first section of logic from the first netlist and a second section of logic from the second cell netlist.Type: GrantFiled: February 19, 2008Date of Patent: February 25, 2014Assignee: Altera CorporationInventors: Gregg William Baeckler, Babette Van Antwerpen
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Patent number: 8429491Abstract: Methods and apparatus are provided for more efficiently implementing error checking code circuitry on a programmable chip. In one example, Cyclic Redundancy Check (CRC) exclusive OR (XOR) circuitry is decomposed to allow efficient implementation on lookup tables (LUTs) of various sizes on a device. XOR cancellation factoring is used to break up wide CRC XORs into blocks that fit in various LUTs while maintaining focus on minimizing logic depth and logic area. Simulated annealing is used to further reduce logic area cost.Type: GrantFiled: November 20, 2009Date of Patent: April 23, 2013Assignee: Altera CorporationInventors: Gregg William Baeckler, Babette Van Antwerpen
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Patent number: 8402408Abstract: An electronic automation system performs register retiming on a logic design, which may be a logic design for a programmable logic integrated circuit. Register retiming is a moving or rearranging of registers across combinatorial logic in a design in order to improve a maximum operating frequency or fmax. In one implementation, the system includes machine-readable code, which may be stored on a computer-readable medium such as a disk, executing on a computer. The system balances timing in order to trade off delays between critical and noncritical paths. Register retiming may make changes to a design at a gate level.Type: GrantFiled: December 28, 2011Date of Patent: March 19, 2013Assignee: Altera CorporationInventors: Babette van Antwerpen, Michael D. Hutton, Gregg Baeckler, Richard Yuan
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Patent number: 8166427Abstract: Circuits, methods, software, and apparatus that track the removal of, reasons for, and consequence of the removal of registers or other circuitry during the synthesis of electronic circuits. An exemplary embodiment of the present invention tracks the removal of registers and determines why the registers were removed. This information is then provided in an efficient manner for design debugging purposes.Type: GrantFiled: March 7, 2008Date of Patent: April 24, 2012Assignee: Altera CorporationInventors: Swatiben Ruturaj Pathak, Babette Van Antwerpen, Michael D. Hutton, Andrew Leaver
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Patent number: 8122396Abstract: Local searches are provided for improving technology mapping for programmable logic integrated circuits. A local search algorithm is applied to a solution for mapping logic gates in a netlist to lookup tables (LUTs) on a programmable logic IC. The local search algorithm applies a series of local moves to the solution. At each move, a small change to the LUT mapping is proposed, and the change in cost for that LUT mapping change is computed. If the cost is improved, the change is accepted and the LUT mapping is replaced by the changed LUT mapping. Otherwise, the change in solution is either rejected, or accepted with a probability that depends on the cost change. The cost function can be chosen to represent one or more features of the LUT mapping, such as area, speed, power consumption, or a combination thereof.Type: GrantFiled: August 26, 2008Date of Patent: February 21, 2012Assignee: Altera CorporationInventor: Babette Van Antwerpen
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Patent number: 8108812Abstract: An electronic automation system performs register retiming on a logic design, which may be a logic design for a programmable logic integrated circuit. Register retiming is a moving or rearranging of registers across combinatorial logic in a design in order to improve a maximum operating frequency or fmax. In one implementation, the system includes machine-readable code, which may be stored on a computer-readable medium such as a disk, executing on a computer. The system balances timing in order to trade off delays between critical and noncritical paths. Register retiming may make changes to a design at a gate level.Type: GrantFiled: March 30, 2010Date of Patent: January 31, 2012Assignee: Altera CorporationInventors: Babette van Antwerpen, Michael D. Hutton, Gregg Baeckler, Richard Yuan
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Patent number: 7945877Abstract: A chain of multiplexers disposed in a logic block is recognized as a selector and a group of logic gates disposed in the logic block and supplying signals to the select pins of the selector is recognized as a decoder, the selector and the decoder together define a n:1 multiplexer. To achieve this, a group of logic gates supplying signals to the select pins of the selector is identified within the logic block. A truth table defining the logic relationship between the signals applied to the group of logic gates and data signals received by the chain of muxes is generated. The chain of muxes is replaced with a selector upon determination that the rows in the truth table are disjoint. After replacing the chain of muxes with a selector, the process is repeated in a similar manner to replace the remaining logic blocks with a decoder.Type: GrantFiled: March 3, 2008Date of Patent: May 17, 2011Assignee: Altera CorporationInventor: Babette Van Antwerpen
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Patent number: 7689955Abstract: An electronic automation system performs register retiming on a logic design, which may be a logic design for a programmable logic integrated circuit. Register retiming is a moving or rearranging of registers across combinatorial logic in a design in order to improve a maximum operating frequency or fmax. In one implementation, the system includes machine-readable code, which may be stored on a computer-readable medium such as a disk, executing on a computer. The system balances timing in order to trade off delays between critical and noncritical paths. Register retiming may make changes to a design at a gate level.Type: GrantFiled: August 30, 2006Date of Patent: March 30, 2010Assignee: Altera CorporationInventors: Babette van Antwerpen, Michael D. Hutton, Gregg Baeckler, Richard Yuan
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Patent number: 7634705Abstract: Methods and apparatus are provided for more efficiently implementing error checking code circuitry on a programmable chip. In one example, Cyclic Redundancy Check (CRC) exclusive OR (XOR) circuitry is decomposed to allow efficient implementation on lookup tables (LUTs) of various sizes on a device. XOR cancellation factoring is used to break up wide CRC XORs into blocks that fit in various LUTs while maintaining focus on minimizing logic depth and logic area. Simulated annealing is used to further reduce logic area cost.Type: GrantFiled: April 12, 2006Date of Patent: December 15, 2009Assignee: Altera CorporationInventors: Gregg William Baeckler, Babette Van Antwerpen
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Patent number: 7594208Abstract: Techniques for optimizing the placement and synthesis of a circuit design on a programmable integrated circuit are provided. The performance of a circuit design is analyzed after it has been compiled with different values for selected input parameters. The input parameter values that produce the best results for an output metric are then chosen to synthesis and place the circuit design on the programmable integrated circuit. In one embodiment, the values of the output metrics are averaged for all test compiles that share the same input parameters, but different seeds. In another embodiment, the compile with the best output metrics, as determined by the user, are selected. These techniques allow a user to automatically trade off compile-time to get a better-optimized circuit.Type: GrantFiled: December 13, 2006Date of Patent: September 22, 2009Assignee: Altera CorporationInventors: Terry Borer, Ian Chesal, James Schleicher, David Mendel, Mike Hutton, Boris Ratchev, Yaska Sankar, Babette van Antwerpen, Gregg Baeckler, Richard Yuan, Stephen Brown, Vaughn Betz, Kevin Chan
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Patent number: 7587688Abstract: Users or applications provide optimization information that specifies performance-critical portions of the design. Users can identify performance-critical portions of their designs from a priori evaluation of their design or by analyzing the results of previous compilations of their design or similar designs. An application may extract and analyze performance information from previous compilations of the design or similar designs to automatically specify the performance-critical portions of the design. The compilation software uses this specification to focus the appropriate types and amount of optimization on different portions of the design. The compilation software may use additional optimization techniques and/or may allocate additional computing resources to optimize the performance of performance-critical portions of the design. Other portions of the design that are not performance-critical may be optimized using balanced optimization techniques.Type: GrantFiled: August 24, 2006Date of Patent: September 8, 2009Assignee: Altera CorporationInventors: Babette Van Antwerpen, Jinyong Yuan, David Karchmer
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Patent number: 7441212Abstract: State machines are identified from a netlist of circuit elements of a user design. Strongly connected components in the netlist are identified as candidates for analysis. The registers of each strongly connected component are identified. An optimal set of inputs and potential state transition logic is identified for the registers in the component. A set of reachable states from an initial state of the registers of a component is determined by simulating state transitions in response to permutations of input values. State machine information is created to assist compilation software in optimizing the user design. Optimizations can include identifying redundant circuit elements based on the set of reachable states and reencoding the state machine with a different state encoding scheme to reduce the amount of state transition and output logic. A subset of the set of reachable states representing a one-hot encoded state machine may be further isolated and optimized.Type: GrantFiled: September 7, 2005Date of Patent: October 21, 2008Assignee: Altera CorporationInventors: Babette van Antwerpen, Gregg William Baeckler
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Patent number: 7418690Abstract: Local searches are provided for improving technology mapping for programmable logic integrated circuits. A local search algorithm is applied to a solution for mapping logic gates in a netlist to lookup tables (LUTs) on a programmable logic IC. The local search algorithm applies a series of local moves to the solution. At each move, a small change to the LUT mapping is proposed, and the change in cost for that LUT mapping change is computed. If the cost is improved, the change is accepted and the LUT mapping is replaced by the changed LUT mapping. Otherwise, the change in solution is either rejected, or accepted with a probability that depends on the cost change. The cost function can be chosen to represent one or more features of the LUT mapping, such as area, speed, power consumption, or a combination thereof.Type: GrantFiled: April 29, 2005Date of Patent: August 26, 2008Assignee: Altera CorporationInventor: Babette Van Antwerpen
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Patent number: 7415693Abstract: A method for designing a system includes caching a representation of a first subnet with a synthesis result of the first subnet. The synthesis result of the first subnet is utilized for a second subnet in response to determining that a representation of the second subnet is identical to the representation of the first subnet.Type: GrantFiled: May 21, 2004Date of Patent: August 19, 2008Assignee: Altera CorporationInventors: Babette van Antwerpen, Gregg William Baeckler, Jinyong Yuan
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Patent number: 7337100Abstract: A multiple-pass synthesis technique improves the performance of a design. In a specific embodiment, synthesis is performed in two or more passes. In a first pass, a first synthesis is performed, and in a second or subsequent pass, a second synthesis or resynthesis is performed. During the first synthesis, the logic will be mapped to for example, the logic structures (e.g., logic elements, LUTs, synthesis gates) of the target technology such as a programmable logic device. Alternatively a netlist may be provided from a third party. Before the second synthesis, a fast or abbreviated fit may be performed of the netlist to a specific device (e.g., specific programmable logic device product). Before the second synthesis, the netlist obtained from the first synthesis (or provided by a third party) is unmapped and then the second synthesis is performed. Since a partial fit is performed, the second synthesis has more visibility and optimize the logic better than by using a single synthesis pass.Type: GrantFiled: June 12, 2003Date of Patent: February 26, 2008Assignee: Altera CorporationInventors: Michael D. Hutton, Joachim Pistorius, Babette van Antwerpen, Gregg Baeckler, Richard Yuan, Yean-Yow Hwang