Patents by Inventor Bahman Hekmatshoartabari

Bahman Hekmatshoartabari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10608111
    Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor layer on an insulating layer, epitaxially growing a first layer on the semiconductor layer, wherein the first layer has a first doping concentration, epitaxially growing a second layer on the semiconductor layer, wherein the second layer has a second doping concentration higher than the first doping concentration, forming a gate dielectric over an active region of the semiconductor layer, forming a gate electrode on the gate dielectric, and forming a plurality of source/drain contacts to the second layer, wherein the first and second layers comprise crystalline hydrogenated silicon (c-Si:H).
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: March 31, 2020
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Ghavam G. Shahidi, Marinus P. J. Hopstaken
  • Patent number: 10593744
    Abstract: An apparatus includes transistor and a set of one or more serially-connected diodes coupled to the transistor. The transistor includes a gate, and first and second terminals. A first diode in the set of serially-connected diodes has a first terminal connected to the second terminal of the transistor. At least one of the diodes includes a first layer including silicon having a first type of carrier as its majority carrier, a first terminal, and a second terminal. The first terminal includes a second layer formed on the first layer, a third layer comprising amorphous hydrogenated silicon having a second type of carrier as its majority carrier formed on the second layer, and a conductive layer formed on the third layer. The second terminal includes a fourth layer comprising crystalline hydrogenated silicon of the first carrier type formed on the first layer, and a conductive layer formed on the fourth layer.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: March 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Ghavam G. Shahidi
  • Patent number: 10586493
    Abstract: A pixel circuit includes a circuit element connected to a gate of a first transistor and ground, which receives a select input. A data line is coupled to a first source/drain of the first transistor, and a second source/drain of the first transistor is coupled to a gate of a second transistor. The second transistor has a drain connected to a supply voltage and a source connected to a resistive element. The resistive element connects to an organic light emitting diode (OLED), which connects to the ground.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Ghavam G. Shahidi
  • Patent number: 10587224
    Abstract: Low-power multi-stage amplifiers are provided for capacitive reading of low-amplitude and low-frequency signals. An exemplary multi-stage amplifier comprises a plurality of amplification stages, wherein each of the amplification stages comprises an amplifying transistor and an active load, wherein substantially all of the amplification stages have one or more of an increasing DC bias level and a decreasing DC bias level relative to a prior stage, and wherein an output of a given one of the amplification stages is directly applied as an input to a subsequent one of the amplification stages.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Ghavam G. Shahidi
  • Patent number: 10585063
    Abstract: A method for making a hydrophobic biosensing device includes forming alternating layers over a top and sides of a fin on a dielectric layer to form a stack of layers. The stack of layers are planarized to expose the top of the fin. The fin and every other layer are removed to form a cathode group of fins and an anode group of fins. A hydrophobic surface on the two groups of fins.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Karthik Balakrishnan, Stephen W. Bedell, Pouya Hashemi, Bahman Hekmatshoartabari, Alexander Reznicek
  • Patent number: 10580926
    Abstract: A multi-junction solar cell comprising a high-crystalline silicon solar cell and a high-crystalline germanium solar cell. The high-crystalline silicon solar including a first p-doped layer and a n+ layer and the high-crystalline germanium solar cell including a second p layer and a heavily doped layer. The multi-junction solar cell can also be comprised of a heavily doped silicon layer on a non-light receiving back surface of the high-crystalline germanium solar cell and a tunnel junction between the high-crystalline silicon solar cell and the high-crystalline germanium solar cell.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: March 3, 2020
    Assignee: International Business Machines Corporation
    Inventors: Anirban Basu, Bahman Hekmatshoartabari, Davood Shahrjerdi
  • Patent number: 10575806
    Abstract: An apparatus (e.g., an imaging system) includes a circuit, including: a p-i-n diode having a cathode coupled to a cathode bias voltage or ground; a charge transistor having a first source/drain terminal coupled to an anode of the diode; a storage capacitor having a first terminal coupled to a second source/drain terminal of the charge transistor and a second terminal coupled to the cathode; an amplification transistor having a gate terminal coupled to the first terminal of the storage capacitor and a first source/drain terminal coupled to a reference voltage; a read transistor having a first source/drain terminal coupled to a second source/drain terminal of the amplification transistor; a data line having a first terminal coupled to a second source/drain terminal of the read transistor; and a readout circuit coupled to a second terminal of the data line, providing an output voltage corresponding to charge on the storage capacitor.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: March 3, 2020
    Assignee: International Business Machines Corporation
    Inventor: Bahman Hekmatshoartabari
  • Publication number: 20200065068
    Abstract: Embodiments are directed to an integrated circuit for a low-power random number generator that uses a thin-film transistor. Embodiments of the integrated circuit include one or more front-end devices formed on a substrate, and one or more interlayer dielectric (ILD) layers formed on the one or more front-end devices. Embodiments of the integrated circuit also include one or more back-end devices formed on the one or more ILD layers, wherein the one or more back-end devices are configured to amplify a noise signal and transmit an amplified noise signal to the one or more front-end devices for processing.
    Type: Application
    Filed: August 22, 2018
    Publication date: February 27, 2020
    Inventors: Bahman Hekmatshoartabari, Ghavam Shahidi
  • Publication number: 20200066795
    Abstract: A multi-layer cross point memory array includes a plurality of layers, each in turn with a plurality of word lines; a plurality of intersecting lines intersecting the word lines at a plurality of points; and a plurality of memory element-transistor stacks. Each of the latter is formed on the intersecting lines; each stack in turn includes a memory element; and a complementary pair of parallel-connected field effect selection transistors including a p-FET and an n-FET, each of which has a gate, a first drain-source terminal connected to a corresponding one of the intersecting lines, and a second drain-source terminal connected to a corresponding one of the memory elements. The gate of the p-FET and the gate of an n-FET in an adjacent stack are connected to the same word line; and the mirror image is true for the n-FET and a p-FET in the adjacent stack on the opposite side.
    Type: Application
    Filed: August 22, 2018
    Publication date: February 27, 2020
    Inventor: Bahman Hekmatshoartabari
  • Patent number: 10573596
    Abstract: A semiconductor structure is provided in which metal semiconductor alloy pillars are formed at least partially within the sidewall surfaces of each semiconductor fin that extends from a surface of a substrate. These pillars are fuses (i.e., FinFET fuses) that are formed at a very tight pitch dimensions. The pillars can be trimmed after forming FinFET devices. The present application provides a method for forming on-chip FinFET fuses easily by choice of the metal semiconductor alloy, the amount of pillar trim, the number of contacted pillars and to a lower design degree the height of each pillar.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: February 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Oscar van der Straten, Praneet Adusumilli, Bahman Hekmatshoartabari
  • Patent number: 10573648
    Abstract: A method for manufacturing a semiconductor device comprises forming a bottom source/drain region on a semiconductor substrate, forming a channel region extending vertically from the bottom source/drain region, growing a top source/drain region from an upper portion of the channel region, and growing a gate region from a lower portion of the channel region under the upper portion, wherein the gate region is on more than one side of the channel region.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: February 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Bahman Hekmatshoartabari, Alexander Reznicek, Jeng-Bang Yau
  • Publication number: 20200058775
    Abstract: A method of manufacturing a vertical transistor device comprises forming a bottom source region on a semiconductor substrate, forming a channel region extending vertically from the bottom source region, forming a top drain region on an upper portion of the channel region, forming a first gate region having a first gate length around the channel region, and forming a second gate region over the first gate region and around the channel region, wherein the second gate region has a second gate length different from the first gate length, and wherein at least one dielectric layer is positioned between the first and second gate regions.
    Type: Application
    Filed: October 23, 2019
    Publication date: February 20, 2020
    Inventors: Karthik Balakrishnan, Bahman Hekmatshoartabari, Alexander Reznicek, Jeng-Bang Yau
  • Publication number: 20200058811
    Abstract: A method for forming a photovoltaic device includes forming a doped layer on a crystalline substrate, the doped layer having an opposite dopant conductivity as the substrate. A non-crystalline transparent conductive electrode (TCE) layer is formed on the doped layer at a temperature less than 150 degrees Celsius. The TCE layer is flash annealed to crystallize material of the TCE layer at a temperature above about 150 degrees Celsius for less than 10 seconds.
    Type: Application
    Filed: October 23, 2019
    Publication date: February 20, 2020
    Inventors: ABDULRAHMAN M. ALBADRI, BAHMAN HEKMATSHOARTABARI, DEVENDRA K. SADANA, KATHERINE L. SAENGER
  • Patent number: 10566976
    Abstract: A complementary circuit, including a logic unit comprising pull-up depletion-mode MOS transistors and pull-down depletion-mode MOS transistors having a single channel type and a level shifting circuit coupled to the logic unit.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: February 18, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bahman Hekmatshoartabari, Ghavam G. Shahidi
  • Publication number: 20200052702
    Abstract: A complementary circuit, including a logic unit which includes pull-up depletion-mode MOS transistors and pull-down depletion-mode MOS transistors and a level shifting circuit coupled to the logic unit.
    Type: Application
    Filed: October 22, 2019
    Publication date: February 13, 2020
    Inventors: Bahman Hekmatshoartabari, Ghavam G. Shahidi
  • Patent number: 10559641
    Abstract: An apparatus includes a junction field-effect transistor (JFET) and a set of one or more serially-connected diodes. The JFET includes a first layer including silicon of a first conductivity type, a gate, and first and second terminals. The gate includes a second layer formed on the first layer and including intrinsic amorphous hydrogenated silicon, a third layer formed on the second layer and including amorphous hydrogenated silicon of a second conductivity type, and a conductive layer formed on the third layer. Each of the first and second terminals includes a fourth layer formed on the first layer, the fourth layer including crystalline hydrogenated silicon of the first conductivity type, and a conductive layer formed on the fourth layer. Each of the serially-connected diodes has first and second terminals, a first of the serially-connected diodes having the first terminal connected to the second terminal of the JFET.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: February 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Ghavam G. Shahidi
  • Patent number: 10553708
    Abstract: A method of manufacturing a vertical transistor device comprises forming a bottom source region on a semiconductor substrate, forming a channel region extending vertically from the bottom source region, forming a top drain region on an upper portion of the channel region, forming a first gate region having a first gate length around the channel region, and forming a second gate region over the first gate region and around the channel region, wherein the second gate region has a second gate length different from the first gate length, and wherein at least one dielectric layer is positioned between the first and second gate regions.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: February 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Bahman Hekmatshoartabari, Alexander Reznicek, Jeng-Bang Yau
  • Patent number: 10553586
    Abstract: A semiconductor device comprises a substrate, a first source/drain region on the substrate, a first channel region extending vertically with respect to the substrate from the first source/drain region, a second source/drain region on the first channel region, a third source/drain region on the second source/drain region, a second channel region extending vertically with respect to the substrate from the third source/drain region, a fourth source/drain region on the second channel region, a first gate region formed around from the first channel region, and a second gate region formed around the second channel region.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: February 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Bahman Hekmatshoartabari, Alexander Reznicek, Jeng-Bang Yau
  • Publication number: 20200035691
    Abstract: VFET-based mask-programmable ROM are provided. In one aspect, a method of forming a ROM device includes: forming a bottom drain on a wafer; forming fins on the bottom drain with a top portion having a channel dopant at a different concentration than a bottom portion of the fins; forming bottom/top dummy gates alongside the bottom/top portions of the fins; forming a source in between the bottom/top dummy gates; forming a top drain above the top dummy gates; removing the bottom/top dummy gates; and replacing the bottom/top dummy gates with bottom/top replacement gates, wherein the bottom drain, the bottom replacement gates, the bottom portion of the fins, and the source form bottom VFETs of the ROM device, and wherein the source, the top replacement gates, the top portion of the fins, and the top drain form top VFETs stacked on the bottom VFETs. A ROM device is also provided.
    Type: Application
    Filed: October 1, 2019
    Publication date: January 30, 2020
    Inventors: Alexander Reznicek, Karthik Balakrishnan, Tak Ning, Bahman Hekmatshoartabari
  • Publication number: 20200027831
    Abstract: A semiconductor structure is provided in which metal semiconductor alloy pillars are formed at least partially within the sidewall surfaces of each semiconductor fin that extends from a surface of a substrate. These pillars are fuses (i.e., FinFET fuses) that are formed at a very tight pitch dimensions. The pillars can be trimmed after forming FinFET devices. The present application provides a method for forming on-chip FinFET fuses easily by choice of the metal semiconductor alloy, the amount of pillar trim, the number of contacted pillars and to a lower design degree the height of each pillar.
    Type: Application
    Filed: September 30, 2019
    Publication date: January 23, 2020
    Inventors: Alexander Reznicek, Oscar van der Straten, Praneet Adusumilli, Bahman Hekmatshoartabari