Patents by Inventor Bahman Hekmatshoartabari

Bahman Hekmatshoartabari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200381480
    Abstract: A method for manufacturing a semiconductor memory device includes forming a first doped semiconductor layer on a conductive layer, forming a second doped semiconductor layer stacked on the first doped semiconductor layer, forming a third doped semiconductor layer stacked on the second doped semiconductor layer, and forming a memory stack layer on the third doped semiconductor layer. The memory stack layer and the first, second and third doped semiconductor layers are patterned into a plurality of pillars spaced apart from each other. In the method, a plurality of extrinsic base layers are formed adjacent the patterned second doped semiconductor layers. The patterned first, second and third doped semiconductor layers in each pillar of the plurality of pillars are components of a bipolar junction transistor device, and the plurality of pillars are parts of a memory cell array having a cross-point structure.
    Type: Application
    Filed: June 3, 2019
    Publication date: December 3, 2020
    Inventors: Alexander Reznicek, Bahman Hekmatshoartabari, Tak H. Ning
  • Publication number: 20200381481
    Abstract: A method for manufacturing a semiconductor memory device includes forming a plurality of doped semiconductor layers in a stacked configuration on a dielectric layer. The plurality of doped semiconductor layers each comprise a single crystalline semiconductor material. In the method, a memory stack layer is formed on an uppermost doped semiconductor layer of the plurality of doped semiconductor layers, and the memory stack layer and a plurality of doped semiconductor layers are patterned into a plurality of pillars spaced apart from each other. The patterned plurality of doped semiconductor layers in each pillar of the plurality of pillars are components of a bipolar junction transistor device, and the plurality of pillars are parts of a memory cell array having a cross-point structure.
    Type: Application
    Filed: June 3, 2019
    Publication date: December 3, 2020
    Inventors: Bahman Hekmatshoartabari, Tak H. Ning, Alexander Reznicek
  • Publication number: 20200373482
    Abstract: Resistive random-access memory cell structures including a first and second resistive random-access memory element stacks, each including an anode and a cathode; a pass transistor having first and second source/drain terminals, and a gate terminal. The gate terminal is connected to the anodes of the first and second resistive random-access memory element stacks. An isolation layer is disposed upon the gate terminal. The isolation layer includes at least two vias, each defined by a perimeter extending from a top surface of the isolation layer to a bottom surface of the isolation layer, each perimeter exposes a portion of the gate. The first and second resistive random-access memory element stacks include a bottom electrode, a switching layer, a top electrode and a low-resistance film. The gate is the bottom electrode. The switching layer, top electrode and low resistance film are disposed in the vias.
    Type: Application
    Filed: May 24, 2019
    Publication date: November 26, 2020
    Inventors: Takashi Ando, Alexander Reznicek, Bahman Hekmatshoartabari
  • Publication number: 20200363393
    Abstract: A biosensor includes a bulk silicon substrate and a vertical bipolar junction transistor (BJT) formed on at least a portion of the substrate. The BJT includes an emitter region, a collector region and an epitaxially grown intrinsic base region between the emitter and collector regions. The biosensor further includes a sensing structure formed on at least a portion of two vertical surfaces of the intrinsic base region of the BJT. The sensing structure includes a channel/trench opening, exposing the intrinsic base region on at least first and second opposing sides thereof, and at least one dielectric layer formed in the channel/trench opening and contacting at least a portion of the intrinsic base region, the dielectric layer being configured to respond to charges in biological molecules.
    Type: Application
    Filed: October 7, 2019
    Publication date: November 19, 2020
    Inventors: Alexander Reznicek, Jeng-Bang Yau, Bahman Hekmatshoartabari
  • Publication number: 20200364032
    Abstract: CMOS-compatible high-speed and low power random number generator and techniques for use thereof are provided. In one aspect, a random number generator includes: a noise amplification unit configured to generate an amplified noise signal, wherein the noise amplification unit includes noise amplification unit transistors having a threshold voltage (Vt,amp) of about 0; and a computing unit configured to process the amplified noise signal from the noise amplification unit to generate a stream of random numbers, wherein the computing unit comprises computing unit transistors having absolute values of a Vt,compute that are larger than the Vt,amp of the noise amplification unit transistors in the noise amplification unit. For digital implementations, an analog-to-digital converter configured to digitize the amplified noise signal can be employed. For analog implementations, a sample and hold circuit configured to sample the amplified noise signal can be employed.
    Type: Application
    Filed: May 14, 2019
    Publication date: November 19, 2020
    Inventors: Bahman Hekmatshoartabari, Ghavam Shahidi
  • Patent number: 10833123
    Abstract: A method for deactivating memory cells affected by the presence of grain boundaries in polycrystalline selection devices includes crystallizing a semiconductor layer in a diode stack to form a polycrystalline layer for selection diodes formed in a crossbar array. To achieve a crystalline state in phase change memory elements coupled to corresponding selection diodes perform an anneal. Memory cells having shunted selection diodes due to grain boundaries are identified by scanning the array using sense voltages. A second voltage larger than the sense voltages is applied to the phase change memory elements gated by the shunted selection diodes such that the phase change memory elements gated by the shunted diodes achieve a permanently high resistive state.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Chung H. Lam, Fabio Carta, Matthew J. BrightSky
  • Publication number: 20200343257
    Abstract: The dosimeter has two vertical field effect transistors (VFETs), each VFET with a bottom and top source/drain and channel between them. An implanted charge storage region material lies between and in contact with each of the vertical channels. A trapped charge is within the implanted charge storage region. The amount of the trapped charge is related to an amount of radiation that passes through the implanted charge storage region.
    Type: Application
    Filed: April 23, 2019
    Publication date: October 29, 2020
    Inventors: Jeng-Bang Yau, Alexander Reznicek, Bahman Hekmatshoartabari, Karthik Balakrishnan
  • Publication number: 20200343266
    Abstract: A method for manufacturing a semiconductor memory device includes forming a first polysilicon layer on a conductive layer, forming a second polysilicon layer stacked on the first polysilicon layer, and forming a third polysilicon layer stacked on the second polysilicon layer. In the method, a stacked structure of the first, second and third polysilicon layers is patterned into a plurality of stacked structures spaced apart from each other on the conductive layer. Ferroelectric dielectric layers are formed on respective second polysilicon layers of the plurality of stacked structures, and metal layers are formed on the ferroelectric dielectric layers.
    Type: Application
    Filed: April 29, 2019
    Publication date: October 29, 2020
    Inventors: Alexander Reznicek, Bahman Hekmatshoartabari
  • Patent number: 10804366
    Abstract: A method is presented for forming a semiconductor device. The method may include forming a first gate structure on a first portion of a semiconductor material located on a surface of an insulating substrate, the first gate structure including a first sacrificial layer and a second sacrificial layer and forming a second gate structure on a second portion of the semiconductor material located on the surface of the insulating substrate, the second gate structure including a third sacrificial layer. The method further includes etching the first and second dielectric sacrificial layers to create a first contact region within the first gate structure and etching the third dielectric sacrificial layer to create a second contact region within the second gate structure. The method further includes forming silicide in at least the first and second contact regions of the first and second gate structures, respectively.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: October 13, 2020
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Bahman Hekmatshoartabari, Ghavam G. Shahidi
  • Publication number: 20200312906
    Abstract: A method of forming an electrical device that includes forming an amorphous semiconductor material on a metal surface of a memory device, in which the memory device is vertically stacked atop a first transistor. The amorphous semiconductor material is annealed with a laser anneal having a nanosecond duration to convert the amorphous semiconductor material into a crystalline semiconductor material. A second transistor is formed from the semiconductor material. The second transistor vertically stacked on the memory device.
    Type: Application
    Filed: March 27, 2019
    Publication date: October 1, 2020
    Inventors: Alexander Reznicek, Bahman Hekmatshoartabari, Oleg Gluschenkov, Yasir Sulehria
  • Publication number: 20200312999
    Abstract: A method of forming an electrical device that includes forming a multilayered fin composed of a first source/drain layer for a first transistor, a first channel layer for the first transistor, a common source/drain layer for the first transistor and a second transistor, a second channel layer for the second transistor and a second source/drain layer for the second transistor. A common spacer is formed on the common source/drain layer that separates a first opening to the first channel layer from a second opening to the second channel layer. Gate structures are then formed in the first and second openings.
    Type: Application
    Filed: March 26, 2019
    Publication date: October 1, 2020
    Inventors: Alexander Reznicek, Bahman Hekmatshoartabari, Tak H. Ning
  • Patent number: 10790336
    Abstract: Hybrid high electron mobility field-effect transistors including inorganic channels and organic gate barrier layers are used in some applications for forming high resolution active matrix displays. Arrays of such high electron mobility field-effect transistors are electrically connected to thin film switching transistors and provide high drive currents for passive devices such as organic light emitting diodes. The organic gate barrier layers are operative to suppress both electron and hole transport between the inorganic channel layer and the gate electrodes of the high electron mobility field-effect transistors.
    Type: Grant
    Filed: April 6, 2019
    Date of Patent: September 29, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Bahman Hekmatshoartabari, Devendra K. Sadana, Davood Shahrjerdi
  • Publication number: 20200303388
    Abstract: A method for manufacturing a semiconductor device includes forming a first vertical transistor on a semiconductor substrate, and forming a second vertical transistor stacked on the first vertical transistor. In the method, a silicide layer is formed on a first drain region of the first vertical transistor and on a second drain region of the second vertical transistor. The silicide layer electrically connects the first and second drain regions to each other.
    Type: Application
    Filed: March 20, 2019
    Publication date: September 24, 2020
    Inventors: Alexander Reznicek, Karthik Balakrishnan, Tak Ning, Bahman Hekmatshoartabari
  • Patent number: 10783334
    Abstract: Systems, methods, and electronic circuits facilitating embedded sensor chips in polymer-based coatings are provided. In one example, a method comprises fabricating an electronic circuit, the electronic circuit comprising one or more semiconductor devices, one or more sensors, and a communication element; encapsulating the electronic circuit within an insulator, resulting in an encapsulated circuit; and dispersing the encapsulated circuit into a lacquer solution comprising a polymer carrier and a solvent.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: September 22, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ali Afzali-Ardakani, Homa Alemzadeh, Maryam Ashoori, Bahman Hekmatshoartabari, Elham Khabiri
  • Patent number: 10777555
    Abstract: A method for manufacturing a semiconductor device comprises forming a bottom source/drain region on a semiconductor substrate, forming a channel region extending vertically from the bottom source/drain region, growing a top source/drain region from an upper portion of the channel region, and growing a gate region from a lower portion of the channel region under the upper portion, wherein the gate region is on more than one side of the channel region.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: September 15, 2020
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Bahman Hekmatshoartabari, Alexander Reznicek, Jeng-Bang Yau
  • Patent number: 10772720
    Abstract: High resolution active matrix nanowire circuits enable a flexible platform for artificial electronic skin having pressure sensing capability. Comb-like interdigitated nanostructures extending vertically from a pair of opposing, flexible assemblies facilitate pressure sensing via changes in resistance caused by varying the extent of contact among the interdigitated nanostructures. Electrically isolated arrays of vertically extending, electrically conductive nanowires or nanofins are formed from a doped, electrically conductive layer, each of the arrays being electrically connected to a transistor in an array of transistors. The nanowires or nanofins are interdigitated with further electrically conductive nanowires or nanofins mounted to a flexible handle.
    Type: Grant
    Filed: May 12, 2018
    Date of Patent: September 15, 2020
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Ghavam G. Shahidi, Davood Shahrjerdi
  • Publication number: 20200279888
    Abstract: A method for manufacturing a semiconductor memory device includes forming a plurality of source lines spaced apart from each other on a dielectric layer, forming a plurality of spacers on sides of the plurality of source lines, and forming a plurality of drain lines on the dielectric layer adjacent the plurality of source lines including the plurality of spacers formed thereon. In the method, a metal oxide layer is formed on the plurality of source lines and on the plurality of drain lines, and a plurality of gate lines are formed on the metal oxide layer. The plurality of gate lines are oriented perpendicular to the plurality of drain lines and the plurality of source lines.
    Type: Application
    Filed: March 1, 2019
    Publication date: September 3, 2020
    Inventors: Bahman Hekmatshoartabari, Alexander Reznicek, Karthik Balakrishnan
  • Patent number: 10763386
    Abstract: A photovoltaic device that includes an upper cell that absorbs a first range of wavelengths of light and a bottom cell that absorbs a second range of wavelengths of light. The bottom cell includes a heterojunction comprising a crystalline germanium containing (Ge) layer. At least one surface of the crystalline germanium (Ge) containing layer is in contact with a silicon (Si) containing layer having a larger band gap than the crystalline (Ge) containing layer.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: September 1, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Keith E. Fogel, Bahman Hekmatshoartabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 10763374
    Abstract: A method is presented for integrating an electronic component in back end of the line (BEOL) processing. The method includes forming a first electrode over a semiconductor substrate, forming a first electrically conductive material over a portion of the first electrode, and forming a second electrically conductive material over the first electrically conductive material, where the first and second electrically conductive materials define a p-n junction. The method further includes depositing a second electrode between a set of spacers and in direct contact with the p-n-junction, depositing a phase change material over the p-n junction and in direct contact with the second electrode, and forming a third electrode over a portion of the phase change material.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: September 1, 2020
    Assignee: International Business Machines Corporation
    Inventors: Fabio Carta, Chung H. Lam, Matthew J. BrightSky, Bahman Hekmatshoartabari
  • Publication number: 20200273967
    Abstract: A method for manufacturing a semiconductor device includes forming a fin on a semiconductor substrate, and forming a bottom source/drain region adjacent a base of the fin. In the method, a dielectric layer, a work function metal layer and a first gate metal layer are sequentially deposited on the bottom source/drain region and around the fin. The dielectric layer, the work function metal layer and the first gate metal layer form a gate structure. The method also includes removing the dielectric layer, the work function metal layer and the first gate metal layer from an end portion of the fin, and depositing a second gate metal layer around the end portion of fin in place of the removed dielectric layer, the removed work function metal layer and the removed first gate metal layer. The second gate metal layer contacts the end portion of the fin.
    Type: Application
    Filed: February 25, 2019
    Publication date: August 27, 2020
    Inventors: Alexander Reznicek, Tak H. Ning, Bahman Hekmatshoartabari, Jeng-Bang Yau