Patents by Inventor Bahman Hekmatshoartabari

Bahman Hekmatshoartabari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11500614
    Abstract: An embodiment of the invention may include a method of forming and a resulting multiply-and-accumulate device. The device may include a capacitor in a second region. The capacitor comprises a dielectric located between a first metal contact and a second metal contact. The device may include a stacked nanosheet device in the first region from the nanosheet. The stacked nanosheet device may include a top transistor and a bottom transistor in contact with the first metal contact. The device may include a nanosheet device in the third region, wherein a source/drain of a transistor of the nanosheet device is in contact with the first metal contact.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: November 15, 2022
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Ruilong Xie, Alexander Reznicek, Jingyun Zhang
  • Patent number: 11489045
    Abstract: Semiconductor channel layers vertically aligned and stacked, separated by a work function metal and a gate dielectric partially surrounding and physically separating the work function metal from each, a first portion of the work function metal directly contacts a vertical sidewall of each layer. A first set and a second set of semiconductor channel layers vertically aligned and stacked, separated by a work function metal, a gate dielectric partially surrounding and physically separating the work function metal from each, a first portion of the work function metal between the first set and the second set directly contacts a sidewall of each layer. Forming an initial stack of alternating layers of a sacrificial and a semiconductor channel vertically aligned and stacked, forming a vertical opening creating a first stack of nanosheet layers and a second stack of nanosheet layers, and exposing vertical side surfaces of the alternating layers of both stacks.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: November 1, 2022
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Ruilong Xie, Bahman Hekmatshoartabari, Tak H. Ning
  • Publication number: 20220336645
    Abstract: A vertical bipolar junction transistor may include an intrinsic base epitaxially grown on a first emitter or collector, the intrinsic base being compositionally graded, a second collector or emitter formed on the intrinsic base, and an extrinsic base formed all-around the intrinsic base. The extrinsic base may be isolated from the first emitter or collector by a first spacer. The extrinsic base may be isolated from the second collector or emitter by a second spacer. The extrinsic base may have a larger bandgap than the intrinsic base. The intrinsic base may be doped with a p-type dopant, and the first emitter or collector, and the second collector or emitter may be doped with an n-type dopant. The first emitter or collector, the intrinsic base, and the second collector or emitter may be made of a III-V semiconductor material.
    Type: Application
    Filed: April 15, 2021
    Publication date: October 20, 2022
    Inventors: Alexander Reznicek, Bahman Hekmatshoartabari, Tak H. Ning, Liying Jiang
  • Publication number: 20220336312
    Abstract: An embodiment of the invention may include a semiconductor structure, method of use and method of manufacture. The structure may include a heating element located underneath a temperature-controlled portion of the device. A method of operating the semiconductor device may include providing current to a thin film heater located beneath a temperature-controlled region of the semiconductor device. The method may include performing temperature dependent operations in the temperature-controlled region.
    Type: Application
    Filed: April 20, 2021
    Publication date: October 20, 2022
    Inventors: Bahman Hekmatshoartabari, Takashi Ando, Nanbo Gong, Alexander Reznicek
  • Patent number: 11476264
    Abstract: A method for manufacturing a semiconductor device includes forming a first vertical transistor on a semiconductor substrate, and forming a second vertical transistor stacked on the first vertical transistor. In the method, a silicide layer is formed on a first drain region of the first vertical transistor and on a second drain region of the second vertical transistor. The silicide layer electrically connects the first and second drain regions to each other.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: October 18, 2022
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Karthik Balakrishnan, Tak Ning, Bahman Hekmatshoartabari
  • Publication number: 20220320282
    Abstract: Semiconductor channel layers vertically aligned and stacked, separated by a work function metal and a gate dielectric partially surrounding and physically separating the work function metal from each, a first portion of the work function metal directly contacts a vertical sidewall of each layer. A first set and a second set of semiconductor channel layers vertically aligned and stacked, separated by a work function metal, a gate dielectric partially surrounding and physically separating the work function metal from each, a first portion of the work function metal between the first set and the second set directly contacts a sidewall of each layer. Forming an initial stack of alternating layers of a sacrificial and a semiconductor channel vertically aligned and stacked, forming a vertical opening creating a first stack of nanosheet layers and a second stack of nanosheet layers, and exposing vertical side surfaces of the alternating layers of both stacks.
    Type: Application
    Filed: March 30, 2021
    Publication date: October 6, 2022
    Inventors: Alexander Reznicek, Ruilong Xie, Bahman Hekmatshoartabari, Tak H. Ning
  • Patent number: 11461645
    Abstract: A memory network can be constructed with at least memory write weightings, memory read weightings and at least one read vector, the memory write weightings parameterizing memory write operations of a neural network to the memory matrix, the memory read weightings parameterizing memory read operations of the neural network from the memory matrix. At least one of the write weightings, the read weightings, or elements of the at least one read vector, can be initialized to have sparsity and/or low discrepancy sampling pattern. The memory network can be trained to perform a task.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: October 4, 2022
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Ravi Nair
  • Patent number: 11456308
    Abstract: A circuit may include a low-voltage flash memory integrated with a vertical field effect transistor and a non-volatile memory element. The low-voltage flash memory may be coupled to the non-volatile memory element by the vertical field effect transistor, one or more bit-lines, and one or more word-lines. The low-voltage flash memory may provide a lower significance conductance and the non-volatile memory element may provide a higher significance conductance. The low-voltage flash memory may include a source and a drain. The source may be separated from the drain by an epitaxial channel. The low-voltage flash memory may include a floating gate. The floating gate may be separated from the epitaxial channel by a first dielectric layer. The low-voltage flash memory may include a control gate. The control gate may be separated from the floating gate by a second dielectric layer.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: September 27, 2022
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Alexander Reznicek, Takashi Ando, Nanbo Gong
  • Patent number: 11424361
    Abstract: A first vertical T-FET has a source heavily doped with a source concentration of a source-type dopant, a drain doped with a drain concentration of a drain-type dopant, and a channel between the source and drain. The source, channel, and drain are stacked vertically in a fin or pillar perpendicular to a substrate. A gate stack encompasses the channel sides and has a drain overlap amount overlapping the drain sides and a source overlap amount overlapping the source sides. External contacts electrically connect the gate and source and/or drain. The source-type dopant and the drain-type dopant are opposite dopant types. In some embodiments, a second vertical T-FET is stacked on the first vertical T-FET. Different VT-FET devices are made by changing the materials, doping types and levels, and connections to the sources, channels, and drains. Device characteristics are designed/changed by changing the amount of source and drain overlaps of the gate stack(s).
    Type: Grant
    Filed: April 10, 2021
    Date of Patent: August 23, 2022
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Bahman Hekmatshoartabari, Alexander Reznicek
  • Patent number: 11411049
    Abstract: A memory device, and a method of making the same, includes a resistive random-access memory element electrically connected to an extrinsic base region of a bipolar junction transistor, the extrinsic base region of the bipolar junction transistor consisting of an epitaxially grown material that forms the bottom electrode of the resistive random-access memory element. Additionally, a method of writing to the memory device includes applying a first voltage on a word line of the memory device to form a filament in the resistive random-access memory element. A second voltage including an opposite polarity to the first voltage can be applied to the word line to remove a portion of the filament in the resistive random-access memory element.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: August 9, 2022
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Bahman Hekmatshoartabari, Ruilong Xie, Heng Wu
  • Patent number: 11374572
    Abstract: A complementary circuit, including a logic unit which includes pull-up depletion-mode MOS transistors and pull-down depletion-mode MOS transistors and a level shifting circuit coupled to the logic unit.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: June 28, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bahman Hekmatshoartabari, Ghavam G. Shahidi
  • Publication number: 20220199688
    Abstract: A memory device, and a method of making the same, includes a resistive random-access memory element electrically connected to an extrinsic base region of a bipolar junction transistor, the extrinsic base region of the bipolar junction transistor consisting of an epitaxially grown material that forms the bottom electrode of the resistive random-access memory element. Additionally, a method of writing to the memory device includes applying a first voltage on a word line of the memory device to form a filament in the resistive random-access memory element. A second voltage including an opposite polarity to the first voltage can be applied to the word line to remove a portion of the filament in the resistive random-access memory element.
    Type: Application
    Filed: December 21, 2020
    Publication date: June 23, 2022
    Inventors: Alexander Reznicek, Bahman Hekmatshoartabari, Ruilong Xie, Heng Wu
  • Publication number: 20220190238
    Abstract: A structure including a bottom electrode, a phase change material layer vertically aligned and an ovonic threshold switching layer vertically aligned above the phase change material layer. A structure including a bottom electrode, a phase change material layer and an ovonic threshold switching layer vertically aligned above the phase change material layer, and a first barrier layer physically separating the ovonic threshold switching layer from a top electrode. A method including forming a structure including a liner vertically aligned above a first barrier layer, the first barrier layer vertically aligned above a phase change material layer, the phase change material layer vertically aligned above a bottom electrode, forming a dielectric surrounding the structure, and forming an ovonic threshold switching layer on the first barrier layer, vertical side surfaces of the first buffer layer are vertically aligned with the first buffer layer, the phase change material layer and the bottom electrode.
    Type: Application
    Filed: December 11, 2020
    Publication date: June 16, 2022
    Inventors: Nanbo Gong, Takashi Ando, ROBERT L. BRUCE, Alexander Reznicek, Bahman Hekmatshoartabari
  • Publication number: 20220189543
    Abstract: A circuit may include a memory cell. The memory cell may include a first memory element, a second memory element, a first transistor, and a second transistor. The first memory element may be connected to a bit line. The second memory element may be connected to a select line. The first transistor may be connected to a first word line. The second transistor may be connected to a second word line. The first memory element may be programmed by applying a first write voltage to the bit line, applying a second write voltage to the second word line, applying a first intermediate voltage to the select line, and applying a second intermediate voltage to the first word line. The select line may be connected to a high impedance. The first write voltage may be a positive supply voltage, the second write voltage may be a negative supply voltage.
    Type: Application
    Filed: December 11, 2020
    Publication date: June 16, 2022
    Inventors: Bahman Hekmatshoartabari, Alexander Reznicek
  • Publication number: 20220181544
    Abstract: A spin-orbit torque (SOT)-MRAM comprising a first magnetic tunneling junction (MTJ) having a first diameter and having a first critical voltage. A second MTJ having a second diameter and having a second critical voltage, wherein the first diameter and the second diameter are different, wherein the first critical voltage and the second critical voltages are different. A metal rail in direct contact with the first MTJ and the second MTJ, wherein the metal rail injects a spin current in to both the first MTJ and the second MTJ.
    Type: Application
    Filed: December 9, 2020
    Publication date: June 9, 2022
    Inventors: Heng Wu, Alexander Reznicek, Bahman Hekmatshoartabari, Jingyun Zhang
  • Publication number: 20220180156
    Abstract: A circuit structure includes a first ferroelectric field effect transistor (FeFET) having a first gate electrode, a first source electrode, and a first drain electrode and a second FeFET having a second gate electrode, a second source electrode, and a second drain electrode. The first gate electrode is connected to a wordline, and the first source electrode and the second source electrode are connected to a bitline. The first drain electrode is connected to the second gate electrode and the second drain electrode is connected to a bias line. A weight synapse structure is constructed by combining two circuit structures. A plurality of weight synapse structures are incorporated into a crossbar array.
    Type: Application
    Filed: December 3, 2020
    Publication date: June 9, 2022
    Inventors: Nanbo Gong, Takashi Ando, Bahman Hekmatshoartabari, Alexander Reznicek
  • Publication number: 20220181388
    Abstract: An approach to forming a semiconductor structure is provided. The semiconductor structure includes two adjacent fins on a substrate. A gate stack is on each of the two adjacent fins. The semiconductor structure includes a first source/drain on a first end of each fin of the two adjacent fins and a second source/drain on a second end of each fin of the two adjacent fins. The semiconductor structure includes a switching layer on at least the first source/drain on the first end of each fin of the two adjacent fins and a top electrode on the switching layer. A metal material over the top electrode in the semiconductor structure.
    Type: Application
    Filed: December 9, 2020
    Publication date: June 9, 2022
    Inventors: Alexander Reznicek, Tsung-Sheng Kang, Takashi Ando, Bahman Hekmatshoartabari
  • Patent number: 11355553
    Abstract: A semiconductor structure may include a vertical field effect transistor, the vertical field effect transistor may include a top source drain, a bottom source drain, and an epitaxial channel and a resistive random access memory below the vertical field effect transistor. The resistive random access memory may include an epitaxial oxide layer, a top electrode, and a bottom electrode. The top electrode, which may function as the bottom source drain of the vertical field effect transistor, may be in direct contact with the epitaxial channel of the vertical field effect transistor. The epitaxial oxide layer may separate the top electrode from the bottom electrode. The top source drain may be arranged between a dielectric material and the epitaxial channel. The dielectric material may be in direct contact with a top surface of the epitaxial channel. The epitaxial oxide layer may be composed of a rare earth oxide.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: June 7, 2022
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Bahman Hekmatshoartabari, Choonghyun Lee, Tak H. Ning
  • Publication number: 20220149183
    Abstract: A semiconductor structure may include one or more metal gates, one or more channels below the one or more metal gates, a gate dielectric layer separating the one or more metal gates from the one or more channels, and a high-k material embedded in the gate dielectric layer. Both the high-k material and the gate dielectric layer may be in direct contact with the one or more channels. The high-k material may provide threshold voltage variation in the one or more metal gates. The high-k material is a first high-k material or a second high-k material. The semiconductor structure may only include the first high-k material embedded in the gate dielectric layer. The semiconductor structure may only include the second high-k material embedded in the gate dielectric layer. The semiconductor structure may include both the first high-k material and the second high-k material embedded in the gate dielectric layer.
    Type: Application
    Filed: November 11, 2020
    Publication date: May 12, 2022
    Inventors: Clint Jason Oteri, Alexander Reznicek, Bahman Hekmatshoartabari, Jingyun Zhang, Ruilong Xie
  • Publication number: 20220149184
    Abstract: A Vertical Reconfigurable Field Effect Transistor (VRFET) has a substrate and a vertical channel. The vertical channel is in contact with a top silicide region that forms a lower Schottky junction with the vertical channel and a top silicide region that forms an upper Schottky junction with the vertical channel. The lower silicide region and the upper silicide region each form a source/drain (S/D) of the device. A lower gate stack surrounds the vertical channel and has a lower overlap that encompasses the lower Schottky junction. An upper gate stack surrounds the vertical channel and has an upper overlap that encompasses the upper Schottky junction. The lower gate stack is electrically insulated from the upper gate stack. The lower gate stack can electrically control the lower Schottky junction (S/D). The upper gate stack can electrically control the upper Schottky junction (S/D).
    Type: Application
    Filed: November 10, 2020
    Publication date: May 12, 2022
    Inventors: Bahman Hekmatshoartabari, Alexander Reznicek