Patents by Inventor Bahman Hekmatshoartabari

Bahman Hekmatshoartabari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11942388
    Abstract: An embodiment of the invention may include a semiconductor structure, method of use and method of manufacture. The structure may include a heating element located underneath a temperature-controlled portion of the device. A method of operating the semiconductor device may include providing current to a thin film heater located beneath a temperature-controlled region of the semiconductor device. The method may include performing temperature dependent operations in the temperature-controlled region.
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: March 26, 2024
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Takashi Ando, Nanbo Gong, Alexander Reznicek
  • Publication number: 20240094801
    Abstract: According to one embodiment, a method, computer system, and computer program product for biometric mixed-reality emotional modification is provided. The present invention may include collecting, by a plurality of biosensors, biometric information on a user during a mixed-reality session, wherein the biometric information comprises biomarkers; identifying, by one or more machine learning models, a mental state of the user based on the biometric information; and responsive to determining that the mental state does not match an intended emotion associated with a mixed-reality experience, modifying the mixed-reality experience with one or more virtual content elements.
    Type: Application
    Filed: September 21, 2022
    Publication date: March 21, 2024
    Inventors: Jeremy R. Fox, Alexander Reznicek, Bahman Hekmatshoartabari, Martin G. Keen
  • Publication number: 20240096012
    Abstract: In an approach to improve the generation of a virtual object in a three-dimensional virtual environment, embodiments of the present invention identify a virtual object to be generated in a three-dimensional virtual environment based on a natural language utterance. Additionally, embodiments generate the virtual object based on a CLIP-guided Generative Latent Space (CLIP-GLS) analysis, and monitor usage of the generated virtual object in the three-dimensional virtual space. Moreover, embodiments infer human perception data from the monitoring, and generate a utility score for the virtual object based on the human perception data.
    Type: Application
    Filed: September 19, 2022
    Publication date: March 21, 2024
    Inventors: Jeremy R. Fox, Martin G. Keen, Alexander Reznicek, Bahman Hekmatshoartabari
  • Patent number: 11929404
    Abstract: A semiconductor structure comprises a gate structure of a transistor. The gate structure comprises a gate conductive portion disposed on a gate dielectric layer. The semiconductor structure further comprises a capacitor structure disposed on the gate structure. The capacitor structure comprises a first conductive layer, a dielectric layer disposed on the first conductive layer and a second conductive layer disposed on the dielectric layer. The first and second conductive layers are respectively connected to a first contact portion and a second contact portion.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: March 12, 2024
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Takashi Ando, Bahman Hekmatshoartabari, Nanbo Gong
  • Publication number: 20240078809
    Abstract: Determining contextual relevance of images to automatically generate notifications is provided. An analysis of an image is performed using a set of machine learning models. A context of a current environment of a user captured in the image is determined based on the analysis of the image. A comparison of the context of the current environment of the user is performed against the known information stored in the knowledge corpus. An insight corresponding to the user activity is generated based on the comparison of the context of the current environment of the user against the known information stored in the knowledge corpus. The insight identifies a set of interested parties corresponding to the user who are to be notified and provides proactive assistance to the user to automatically generate a notification in real time. The notification is generated containing the insight corresponding to the user activity.
    Type: Application
    Filed: September 6, 2022
    Publication date: March 7, 2024
    Inventors: Martin G. Keen, Jeremy R. Fox, Alexander Reznicek, Bahman Hekmatshoartabari
  • Patent number: 11910734
    Abstract: A structure including a bottom electrode, a phase change material layer vertically aligned and an ovonic threshold switching layer vertically aligned above the phase change material layer. A structure including a bottom electrode, a phase change material layer and an ovonic threshold switching layer vertically aligned above the phase change material layer, and a first barrier layer physically separating the ovonic threshold switching layer from a top electrode. A method including forming a structure including a liner vertically aligned above a first barrier layer, the first barrier layer vertically aligned above a phase change material layer, the phase change material layer vertically aligned above a bottom electrode, forming a dielectric surrounding the structure, and forming an ovonic threshold switching layer on the first barrier layer, vertical side surfaces of the first buffer layer are vertically aligned with the first buffer layer, the phase change material layer and the bottom electrode.
    Type: Grant
    Filed: May 4, 2023
    Date of Patent: February 20, 2024
    Assignee: International Business Machines Corporation
    Inventors: Nanbo Gong, Takashi Ando, Robert L. Bruce, Alexander Reznicek, Bahman Hekmatshoartabari
  • Patent number: 11901449
    Abstract: A method of forming an electrical device that includes forming a multilayered fin composed of a first source/drain layer for a first transistor, a first channel layer for the first transistor, a common source/drain layer for the first transistor and a second transistor, a second channel layer for the second transistor and a second source/drain layer for the second transistor. A common spacer is formed on the common source/drain layer that separates a first opening to the first channel layer from a second opening to the second channel layer. Gate structures are then formed in the first and second openings.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: February 13, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alexander Reznicek, Bahman Hekmatshoartabari, Tak H. Ning
  • Patent number: 11894444
    Abstract: A semiconductor structure may include one or more metal gates, one or more channels below the one or more metal gates, a gate dielectric layer separating the one or more metal gates from the one or more channels, and a high-k material embedded in the gate dielectric layer. Both the high-k material and the gate dielectric layer may be in direct contact with the one or more channels. The high-k material may provide threshold voltage variation in the one or more metal gates. The high-k material is a first high-k material or a second high-k material. The semiconductor structure may only include the first high-k material embedded in the gate dielectric layer. The semiconductor structure may only include the second high-k material embedded in the gate dielectric layer. The semiconductor structure may include both the first high-k material and the second high-k material embedded in the gate dielectric layer.
    Type: Grant
    Filed: December 6, 2022
    Date of Patent: February 6, 2024
    Assignee: International Business Machines Corporation
    Inventors: Clint Jason Oteri, Alexander Reznicek, Bahman Hekmatshoartabari, Jingyun Zhang, Ruilong Xie
  • Patent number: 11889774
    Abstract: A structure including a bottom electrode, a phase change material layer, the phase change material layer includes a similar lattice constant as a lattice constant of the substrate, a top electrode on and vertically aligned with the phase change material layer, a dielectric material horizontally isolating the bottom electrode from the top electrode and the phase change material layer. A structure including a phase change material layer selected from amorphous silicon, amorphous germanium and amorphous silicon germanium, a top electrode on the phase change material layer, a bottom electrode, a dielectric material isolating the bottom electrode from the top electrode and the phase change material layer. Forming a bottom electrode, forming a phase change material layer adjacent to the bottom electrode, forming a top electrode above the phase change material, forming a dielectric material horizontally isolating the bottom electrode from the top electrode and the phase change material layer.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: January 30, 2024
    Assignee: International Business Machines Corporation
    Inventors: Devendra K. Sadana, Ning Li, Bahman Hekmatshoartabari
  • Patent number: 11869983
    Abstract: A Junction Field Effect Transistor (JFET) has a source and a drain disposed on a substrate. The source and drain have an S/D doping with an S/D doping type. Two or more channels are electrically connected in parallel between the source and drain and can carry a current between the source and drain. Each of the channels has two or more channel surfaces. The channel has the same channel doping type as the S/D doping type. A first gate is in direct contact with one of the channel surfaces. One or more second gates is in direct contact with a respective second channel surface. The gates are doped with a gate doping that has a gate doping type opposite of the channel doping type. A p-n junction (junction gate) is formed where the gates and channel surfaces are in direct contact. The first and second gates are electrically connected so a voltage applied to the first and second gates creates at least two depletion regions in each of the channels.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: January 9, 2024
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Bahman Hekmatshoartabari, Karthik Balakrishnan
  • Publication number: 20230412765
    Abstract: Methods, systems, and a computer program product are disclosed. The first method includes obtaining virtual session data in real time, identifying a positional utterance in the virtual session data, and generating a positional insight for the positional utterance. The first method also includes rendering a user avatar in a position recommended based on the positional insight. The second method includes obtaining virtual session data in real time, identifying a positional utterance in the virtual session data, and generating positional insights for the positional utterance. The second method also includes generating at least one position recommendation based on the positional insights.
    Type: Application
    Filed: June 20, 2022
    Publication date: December 21, 2023
    Inventors: Martin G. Keen, Jeremy R. Fox, Alexander Reznicek, Bahman Hekmatshoartabari
  • Publication number: 20230410435
    Abstract: Methods, systems, and a computer program product are disclosed. The first method includes obtaining virtual session data in real time, identifying a positional utterance in the virtual session data, and generating a positional insight for the positional utterance. The first method also includes generating a best-practices recommendation based on the positional insight. The second method includes obtaining virtual session data, identifying positional utterances in the virtual session data, and generating positional insights for each of the positional utterances. The second method also includes selecting each of the positional insights having confidence scores above a threshold score and generating best-practices recommendations based on the selected positional insights.
    Type: Application
    Filed: June 20, 2022
    Publication date: December 21, 2023
    Inventors: Martin G. Keen, Jeremy R. Fox, Alexander Reznicek, Bahman Hekmatshoartabari
  • Patent number: 11818886
    Abstract: A method of manufacturing a low program voltage flash memory cell with an embedded heater in the control gate creates, on a common device substrate, a conventional flash memory cell in a conventional flash memory area (CFMA), and a neuromorphic computing memory cell in a neuromorphic computing memory area (NCMA). The method comprises providing a flash memory stack in both the CFMA and the NCMA, depositing a heater on top of the flash memory stack in the NCMA without depositing a heater on top of the flash memory stack in the CFMA.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: November 14, 2023
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Nanbo Gong, Bahman Hekmatshoartabari, Alexander Reznicek
  • Patent number: 11800698
    Abstract: Techniques for fabricating semiconductor structures and devices with stacked structures having embedded capacitors are disclosed. In one example, a semiconductor structure includes a substrate having a first region and a second region. The semiconductor structure further includes a capacitor structure disposed in the second region of the substrate. The capacitor structure includes a capacitor conductor and a dielectric insulator disposed between the capacitor conductor and the substrate. The semiconductor structure further includes a stacked device disposed on the first region of the substrate. The stacked device includes a first transistor and a second transistor. At least a portion of the second transistor is disposed under at least a portion of the first transistor. The first transistor and the second transistor are each coupled to the capacitor conductor.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: October 24, 2023
    Assignee: International Business Machines Corporation
    Inventors: Ruilong Xie, Takashi Ando, Alexander Reznicek, Bahman Hekmatshoartabari
  • Publication number: 20230309422
    Abstract: A structure including a bottom electrode, a phase change material layer vertically aligned and an ovonic threshold switching layer vertically aligned above the phase change material layer. A structure including a bottom electrode, a phase change material layer and an ovonic threshold switching layer vertically aligned above the phase change material layer, and a first barrier layer physically separating the ovonic threshold switching layer from a top electrode. A method including forming a structure including a liner vertically aligned above a first barrier layer, the first barrier layer vertically aligned above a phase change material layer, the phase change material layer vertically aligned above a bottom electrode, forming a dielectric surrounding the structure, and forming an ovonic threshold switching layer on the first barrier layer, vertical side surfaces of the first buffer layer are vertically aligned with the first buffer layer, the phase change material layer and the bottom electrode.
    Type: Application
    Filed: May 4, 2023
    Publication date: September 28, 2023
    Inventors: Nanbo Gong, Takashi Ando, Robert L. Bruce, Alexander Reznicek, Bahman Hekmatshoartabari
  • Publication number: 20230260990
    Abstract: A sensor device includes a vertically stacked cascode bipolar junction transistor pair, and a first trench having a first sidewall, wherein a portion of the first sidewall is provided by the first sensing surface, wherein a bipolar junction transistor and a dual-base bipolar junction transistor of the cascode bipolar junction transistor pair are stacked vertically along the first trench.
    Type: Application
    Filed: February 16, 2022
    Publication date: August 17, 2023
    Inventors: Alexander Reznicek, Bahman Hekmatshoartabari
  • Patent number: 11697889
    Abstract: A structure including a three-dimensionally stretchable single crystalline semiconductor membrane located on a substrate is provided. The structure is formed by providing a three-dimensional (3D) wavy silicon germanium alloy layer on a silicon handler substrate. A single crystalline semiconductor material membrane is then formed on a physically exposed surface of the 3D wavy silicon germanium alloy layer. A substrate is then formed on a physically exposed surface of the single crystalline semiconductor material membrane. The 3D wavy silicon germanium alloy layer and the silicon handler substrate are thereafter removed providing the structure.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: July 11, 2023
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Karthik Balakrishnan, Stephen W. Bedell, Pouya Hashemi, Bahman Hekmatshoartabari, Keith E. Fogel
  • Patent number: 11695004
    Abstract: A semiconductor device or circuit includes a vertical bipolar junction transistor (vBJT) and a vertical filed effect transistor (vFET). The vBJT collector is electrically and/or physically connected to an adjacent vFET source. For example, a vBJT collector and a vFET source may be integrated upon a same semiconductor material substrate or layer. The vFET provides negative feedback for the collector-base voltage and the vBJT emitter and collector allow for low transit times.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: July 4, 2023
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Ruilong Xie, Jeng-Bang Yau, Bahman Hekmatshoartabari
  • Patent number: 11683941
    Abstract: A semiconductor structure may include two vertical transport field effect transistors comprising a top source drain, a bottom source drain, and an epitaxial channel and a resistive random access memory between the two vertical transport field effect transistors, the resistive random access memory may include an oxide layer, a top electrode, and a bottom electrode, wherein the oxide layer may contact the top source drain of the two vertical field effect transistor. The top source drain may function as the bottom electrode of the resistive random access memory. The semiconductor structure may include a shallow trench isolation between the two vertical transport field effect transistors, the shallow trench isolation may be embedded in a first spacer, a doped source, and a portion of a substrate.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: June 20, 2023
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Karthik Balakrishnan, Bahman Hekmatshoartabari, Takashi Ando
  • Patent number: 11682718
    Abstract: A vertical bipolar junction transistor may include an intrinsic base epitaxially grown on a first emitter or collector, the intrinsic base being compositionally graded, a second collector or emitter formed on the intrinsic base, and an extrinsic base formed all-around the intrinsic base. The extrinsic base may be isolated from the first emitter or collector by a first spacer. The extrinsic base may be isolated from the second collector or emitter by a second spacer. The extrinsic base may have a larger bandgap than the intrinsic base. The intrinsic base may be doped with a p-type dopant, and the first emitter or collector, and the second collector or emitter may be doped with an n-type dopant. The first emitter or collector, the intrinsic base, and the second collector or emitter may be made of a III-V semiconductor material.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: June 20, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alexander Reznicek, Bahman Hekmatshoartabari, Tak H. Ning, Liying Jiang