Patents by Inventor Bahman Hekmatshoartabari

Bahman Hekmatshoartabari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11189701
    Abstract: Vertical bipolar junction transistors (VBJTs), each with one or more resistors connected in a circuit in different circuit configurations, are disclosed. The VBJT has an emitter substructure that includes an emitter layer, a collector, an intrinsic base, one or more doped epitaxy regions, and one or more resistors. The intrinsic base, the doped epitaxy region(s), and the resistor(s) are stacked upon one another in a channel between the emitter layer and the collector. Various circuit configurations and structures are described including a common-collector circuit, a common-emitter circuit, and an emitter-degenerate circuit. Methods of making these configuration/structures are disclosed.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: November 30, 2021
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Bahman Hekmatshoartabari, Karthik Balakrishnan
  • Patent number: 11187672
    Abstract: A method for making a hydrophobic biosensing device includes forming alternating layers over a top and sides of a fin on a dielectric layer to form a stack of layers. The stack of layers are planarized to expose the top of the fin. The fin and every other layer are removed to form a cathode group of fins and an anode group of fins. A hydrophobic surface on the two groups of fins.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: November 30, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ali Afzali-Ardakani, Karthik Balakrishnan, Stephen W. Bedell, Pouya Hashemi, Bahman Hekmatshoartabari, Alexander Reznicek
  • Publication number: 20210365819
    Abstract: An apparatus for performing fuzzy template matching includes multiple damped oscillators arranged in at least one two-dimensional matrix, each of the damped oscillators being capacitively coupled to at least one adjacent damped oscillator in the matrix. The apparatus further includes peripheral circuitry coupled with the damped oscillators. The peripheral circuitry is configured to selectively interface with the damped oscillators, as a function of one or more control signals supplied to the peripheral circuitry, and to generate at least one output signal indicative of an accuracy of matching between a template pattern and an input pattern.
    Type: Application
    Filed: May 22, 2020
    Publication date: November 25, 2021
    Inventor: Bahman Hekmatshoartabari
  • Patent number: 11182670
    Abstract: A classifier system implementing an equivalent deep neural network (DNN) includes a weight block, classification block, row selector, and sensor array coupled with the weight block, classification block and row selector. The sensor array includes row lines, column lines, a data integration line, an integration start line, and multiple sensor cells corresponding to respective neurons in an input layer of the equivalent DNN. The sensor cells share a common terminal connected to the data integration line, the row lines are controlled by the row selector, and the column lines receive respective weight values from the weight block. The classification block includes a first integrator receiving a signal generated on the data integration line when the integration start line is selected, and a first thresholding unit receiving a signal from the first integrator. The first thresholding unit is coupled to second integrators and second thresholding units arranged in a two-dimensional matrix.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: November 23, 2021
    Assignee: International Business Machines Corporation
    Inventor: Bahman Hekmatshoartabari
  • Patent number: 11183115
    Abstract: A method for forming a pixel circuit includes forming transistors on a substrate; forming a passivation layer over the transistors; forming a contact hole to a source of a transistor; forming a transparent conductor that forms a contact in the contact hole and a resistor to control pixel current; and forming an organic light emitting diode (OLED) with an anode connecting to the resistor.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: November 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bahman Hekmatshoartabari, Ghavam G. Shahidi
  • Patent number: 11177225
    Abstract: Fabrication of a physically unclonable function containing semiconductor device by fabricating a first electrode of the semiconductor device, randomly nucleating material regions upon a surface of the first electrode and forming a second electrode upon the first electrode and at least a portion of the randomly nucleated regions.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: November 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Takashi Ando, Alexander Reznicek, Nanbo Gong
  • Publication number: 20210349691
    Abstract: An embodiment of the invention may include a method of forming and a resulting multiply-and-accumulate device. The device may include a capacitor in a second region. The capacitor comprises a dielectric located between a first metal contact and a second metal contact. The device may include a stacked nanosheet device in the first region from the nanosheet. The stacked nanosheet device may include a top transistor and a bottom transistor in contact with the first metal contact. The device may include a nanosheet device in the third region, wherein a source/drain of a transistor of the nanosheet device is in contact with the first metal contact.
    Type: Application
    Filed: May 11, 2020
    Publication date: November 11, 2021
    Inventors: Bahman Hekmatshoartabari, Ruilong Xie, Alexander Reznicek, Jingyun Zhang
  • Patent number: 11164907
    Abstract: A method may include forming two vertical transport field effect transistors stacked one atop the other and separated by a resistive random access memory structure. The two vertical transport field effect transistors may include a source, a channel, and a drain, wherein a contact layer of the resistive random access memory structure functions as the drain of the two vertical transport field effect transistors. Forming the two vertical transport field effect transistors may further include forming a first source and a second source. The first source is a bottom source and the second source is a top source. The method may include forming a gate conductor layer surrounding the channel. The resistive random access memory structures may include faceted epitaxy defined by pointed tips. The pointed tips of the faceted epitaxy may extend vertically toward each other. The faceted epitaxy may be between the two vertical transport field effect transistors.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: November 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Bahman Hekmatshoartabari, Alexander Reznicek, Takashi Ando
  • Publication number: 20210336128
    Abstract: A memory device is provided that includes at least one MTJ pillar which can have a ternary program state as compared to a binary program state in a conventional device. The MTJ pillar contains a lower MTJ structure that includes at least a first magnetic reference material, a first tunnel barrier and a first magnetic free layer material, and an upper MTJ structure that includes at least a second magnetic reference material, a second tunnel barrier and a second magnetic free layer material; the upper MTJ structure is stacked atop the lower MTJ structure. The first and second magnetic free layer materials have different designs and/or compositions resulting in different switching voltages.
    Type: Application
    Filed: April 24, 2020
    Publication date: October 28, 2021
    Inventors: Alexander Reznicek, Bahman Hekmatshoartabari, Michael Rizzolo, Ravi Nair
  • Patent number: 11158756
    Abstract: A semiconductor radiation monitor (i.e., dosimeter) is provided that has an oxide charge storage region located on a first side of a semiconductor fin and a functional gate structure located on a second side of the semiconductor fin that is opposite the first side. Charges are created in the oxide charge storage region that is located on the first side of the semiconductor fin and detected on the second side of the semiconductor fin by the functional gate structure. Multiple semiconductor fins in parallel can form a dense and very sensitive semiconductor radiation monitor.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: October 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Bahman Hekmatshoartabari, Jeng-Bang Yau, Karthik Balakrishnan
  • Publication number: 20210320205
    Abstract: A Vertical Junction Field Effect Transistor (VJFET) is disclosed with reduced noise and input capacitance and high input impedance. The VJFET has a substrate; a source disposed on the substrate; a drain; and a channel. The vertical channel has one or more channel sidewall surfaces. The channel sidewall surfaces have a total or aggregate channel sidewall surface area. A semiconductor gate grown on one or more of the channel sidewall surfaces has a thickness below 10 nanometers (nm), or between 3 nm and 10 nm, that reduces transistor noise. The interface surface area between the conductive (e.g. metal) external electrical gate contact and the contacted surface of the semiconductor gate is minimized to further reduce transistor noise.
    Type: Application
    Filed: April 8, 2020
    Publication date: October 14, 2021
    Inventors: Bahman Hekmatshoartabari, Alexander Reznicek, Karthik Balakrishnan
  • Patent number: 11145816
    Abstract: A one-transistor-two-resistor (1T2R) resistive random access memory (ReRAM) structure, and a method for forming the same, includes forming a vertical field effect transistor (VFET) including an epitaxial region located above a channel region and below a dielectric cap. The epitaxial region includes two opposing protruding regions of triangular shape bounded by <111> planes that extend horizontally beyond the channel region. A ReRAM stack is conformally deposited on the VFET. The ReRAM stack includes an oxide layer located directly above the epitaxial region, a top electrode layer directly above the oxide layer and a metal fill above the top electrode layer. Each of the two opposing protruding regions of the epitaxial region acts as a bottom electrode for the ReRAM stack.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: October 12, 2021
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Bahman Hekmatshoartabari, Takashi Ando, Karthik Balakrishnan
  • Patent number: 11145769
    Abstract: A method for forming a photovoltaic device includes forming a doped layer on a crystalline substrate, the doped layer having an opposite dopant conductivity as the substrate. A non-crystalline transparent conductive electrode (TCE) layer is formed on the doped layer at a temperature less than 150 degrees Celsius. The TCE layer is flash annealed to crystallize material of the TCE layer at a temperature above about 150 degrees Celsius for less than 10 seconds.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: October 12, 2021
    Assignees: International Business Machines Corporation, KING ABDULAZIZ CITY FOR SCIENCE AND TECHNOLOGY
    Inventors: Abdulrahman M. Albadri, Bahman Hekmatshoartabari, Devendra K. Sadana, Katherine L. Saenger
  • Patent number: 11132177
    Abstract: CMOS-compatible high-speed and low power random number generator and techniques for use thereof are provided. In one aspect, a random number generator includes: a noise amplification unit configured to generate an amplified noise signal, wherein the noise amplification unit includes noise amplification unit transistors having a threshold voltage (Vt,amp) of about 0; and a computing unit configured to process the amplified noise signal from the noise amplification unit to generate a stream of random numbers, wherein the computing unit comprises computing unit transistors having absolute values of a Vt,compute that are larger than the Vt,amp of the noise amplification unit transistors in the noise amplification unit. For digital implementations, an analog-to-digital converter configured to digitize the amplified noise signal can be employed. For analog implementations, a sample and hold circuit configured to sample the amplified noise signal can be employed.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: September 28, 2021
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Ghavam Shahidi
  • Publication number: 20210288109
    Abstract: A method may include forming two vertical transport field effect transistors stacked one atop the other and separated by a resistive random access memory structure. The two vertical transport field effect transistors may include a source, a channel, and a drain, wherein a contact layer of the resistive random access memory structure functions as the drain of the two vertical transport field effect transistors. Forming the two vertical transport field effect transistors may further include forming a first source and a second source. The first source is a bottom source and the second source is a top source. The method may include forming a gate conductor layer surrounding the channel. The resistive random access memory structures may include faceted epitaxy defined by pointed tips. The pointed tips of the faceted epitaxy may extend vertically toward each other. The faceted epitaxy may be between the two vertical transport field effect transistors.
    Type: Application
    Filed: March 11, 2020
    Publication date: September 16, 2021
    Inventors: Karthik Balakrishnan, Bahman Hekmatshoartabari, Alexander Reznicek, Takashi Ando
  • Publication number: 20210288187
    Abstract: A Junction Field Effect Transistor (JFET) has a source and a drain disposed on a substrate. The source and drain have an S/D doping with an S/D doping type. Two or more channels are electrically connected in parallel between the source and drain and can carry a current between the source and drain. Each of the channels has two or more channel surfaces. The channel has the same channel doping type as the S/D doping type. A first gate is in direct contact with one of the channel surfaces. One or more second gates is in direct contact with a respective second channel surface. The gates are doped with a gate doping that has a gate doping type opposite of the channel doping type. A p-n junction (junction gate) is formed where the gates and channel surfaces are in direct contact. The first and second gates are electrically connected so a voltage applied to the first and second gates creates at least two depletion regions in each of the channels.
    Type: Application
    Filed: March 12, 2020
    Publication date: September 16, 2021
    Inventors: Alexander Reznicek, Bahman Hekmatshoartabari, Karthik Balakrishnan
  • Patent number: 11114146
    Abstract: An erasable magnetoresistive random-access memory (MRAM) structure and a method of making the same includes an MRAM cell disposed between bit line and word line circuit elements, and a vertical-cavity surface-emitting laser (VCSEL) element disposed above the MRAM cell. A laser output of the VCSEL is directed toward the MRAM cell.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: September 7, 2021
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Eric Raymond Evarts, Virat Vasav Mehta, Bahman Hekmatshoartabari
  • Publication number: 20210272857
    Abstract: A first vertical T-FET has a source heavily doped with a source concentration of a source-type dopant, a drain doped with a drain concentration of a drain-type dopant, and a channel between the source and drain. The source, channel, and drain are stacked vertically in a fin or pillar perpendicular to a substrate. A gate stack encompasses the channel sides and has a drain overlap amount overlapping the drain sides and a source overlap amount overlapping the source sides. External contacts electrically connect the gate and source and/or drain. The source-type dopant and the drain-type dopant are opposite dopant types. In some embodiments, a second vertical T-FET is stacked on the first vertical T-FET. Different VT-FET devices are made by changing the materials, doping types and levels, and connections to the sources, channels, and drains. Device characteristics are designed/changed by changing the amount of source and drain overlaps of the gate stack(s).
    Type: Application
    Filed: April 10, 2021
    Publication date: September 2, 2021
    Inventors: Karthik Balakrishnan, Bahman Hekmatshoartabari, Alexander Reznicek
  • Patent number: 11101374
    Abstract: One or more gated nanosheet diodes are disposed on a substrate and made from a nanosheet structure. A first (second) source/drain (S/D) is disposed on the substrate. The first (second) S/D has a first (second) S/D doping concentration with a first (second) S/D doping type. One or more p-n junctions form one or more respective diodes. There is a first side and a second side of each of the p-n junctions. The first (second) sides of the p-n junctions electrically and physically connect to the first (second) S/Ds and have the same type of doping, respectively. A gate stack, made of a gate dielectric layer and a gate metal, interfaces and surrounds each of the p-n junctions.
    Type: Grant
    Filed: June 13, 2020
    Date of Patent: August 24, 2021
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Bahman Hekmatshoartabari, Karthik Balakrishnan
  • Patent number: 11101290
    Abstract: A method for manufacturing a semiconductor memory device includes forming a first polysilicon layer on a conductive layer, forming a second polysilicon layer stacked on the first polysilicon layer, and forming a third polysilicon layer stacked on the second polysilicon layer. In the method, a stacked structure of the first, second and third polysilicon layers is patterned into a plurality of stacked structures spaced apart from each other on the conductive layer. Ferroelectric dielectric layers are formed on respective second polysilicon layers of the plurality of stacked structures, and metal layers are formed on the ferroelectric dielectric layers.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: August 24, 2021
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Bahman Hekmatshoartabari