Patents by Inventor Bala S. Haran

Bala S. Haran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10991689
    Abstract: A method includes forming a first region including a pair of first FinFETs and a second region including a pair of second FinFETs on a substrate. Each FinFET includes a metal gate having a first spacer adjacent thereto, and each first FinFET has a gate dielectric that is thicker than a gate dielectric of each second FinFET, such that the first FinFETs can be higher voltage input/output devices. The method forms a first contact between the metal gates of the pair of first FinFETs with a second spacer thereabout, the second spacer contacting a portion of each first spacer. The second spacer thus has a portion extending parallel to the metal gates, and a portion extending perpendicular to the metal gates. A second contact is formed between the metal gates of the pair of second FinFETs, and the second contact devoid of the second spacer.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: April 27, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Abu Naser M. Zainuddin, Christopher D. Sheraw, Sangameshwar Rao Saudari, Wei Ma, Kai Zhao, Bala S Haran
  • Publication number: 20200321332
    Abstract: A method includes forming a first region including a pair of first FinFETs and a second region including a pair of second FinFETs on a substrate. Each FinFET includes a metal gate having a first spacer adjacent thereto, and each first FinFET has a gate dielectric that is thicker than a gate dielectric of each second FinFET, such that the first FinFETs can be higher voltage input/output devices. The method forms a first contact between the metal gates of the pair of first FinFETs with a second spacer thereabout, the second spacer contacting a portion of each first spacer. The second spacer thus has a portion extending parallel to the metal gates, and a portion extending perpendicular to the metal gates. A second contact is formed between the metal gates of the pair of second FinFETs, and the second contact devoid of the second spacer.
    Type: Application
    Filed: April 5, 2019
    Publication date: October 8, 2020
    Inventors: Abu Naser M. Zainuddin, Christopher D. Sheraw, Sangameshwar Rao Saudari, Wei Ma, Kai Zhao, Bala S. Haran
  • Patent number: 8691687
    Abstract: In accordance with one aspect of the invention, a method is provided for fabricating a semiconductor element having a contact via. In such method, a hole can be formed in a dielectric layer to at least partially expose a region including at least one of semiconductor or conductive material. A seed layer can be deposited over a major surface of the dielectric layer and over a surface within the hole. In one embodiment, the seed layer can include a metal selected from the group consisting of iridium, osmium, palladium, platinum, rhodium, and ruthenium. A layer consisting essentially of cobalt can be electroplated over the seed layer within the hole to form a contact via in electrically conductive communication with the region.
    Type: Grant
    Filed: January 7, 2010
    Date of Patent: April 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: James J. Kelly, Veeraghavan S. Basker, Bala S. Haran, Soon-Cheon Seo, Tuan A. Vo
  • Patent number: 8673699
    Abstract: A method of forming a semiconductor structure which includes an extremely thin silicon-on-insulator (ETSOI) semiconductor structure having a PFET portion and an NFET portion, a gate structure in the PFET portion and the NFET portion, a high quality nitride spacer adjacent to the gate structures in the PFET portion and the NFET portion and a doped faceted epitaxial silicon germanium raised source/drain (RSD) in the PFET portion. An amorphous silicon layer is formed on the RSD in the PFET portion. A faceted epitaxial silicon RSD is formed on the ETSOI adjacent to the high quality nitride in the NFET portion. The amorphous layer in the PFET portion prevents epitaxial growth in the PFET portion during formation of the RSD in the NFET portion. Extensions are ion implanted into the ETSOI underneath the gate structure in the NFET portion.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: March 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Thomas N. Adam, Kangguo Cheng, Bruce B. Doris, Bala S. Haran, Pranita Kulkarni, Amlan Majumdar, Stefan Schmitz
  • Publication number: 20140024181
    Abstract: A method of forming a semiconductor structure which includes an extremely thin silicon-on-insulator (ETSOI) semiconductor structure having a PFET portion and an NFET portion, a gate structure in the PFET portion and the NFET portion, a high quality nitride spacer adjacent to the gate structures in the PFET portion and the NFET portion and a doped faceted epitaxial silicon germanium raised source/drain (RSD) in the PFET portion. An amorphous silicon layer is formed on the RSD in the PFET portion. A faceted epitaxial silicon RSD is formed on the ETSOI adjacent to the high quality nitride in the NFET portion. The amorphous layer in the PFET portion prevents epitaxial growth in the PFET portion during formation of the RSD in the NFET portion. Extensions are ion implanted into the ETSOI underneath the gate structure in the NFET portion.
    Type: Application
    Filed: July 17, 2012
    Publication date: January 23, 2014
    Applicant: International Business Machines Corporation
    Inventors: Thomas N. Adam, Kangguo Cheng, Bruce B. Doris, Bala S. Haran, Pranita Kulkarni, Amlan Majumdar, Stefan Schmitz
  • Patent number: 8546203
    Abstract: Method of forming a semiconductor structure which includes an extremely thin silicon-on-insulator (ETSOI) semiconductor structure having a PFET portion and an NFET portion, a gate structure in the PFET portion and the NFET portion, a high quality nitride spacer adjacent to the gate structures in the PFET portion and the NFET portion and a doped faceted epitaxial silicon germanium raised source/drain (RSD) in the PFET portion. Low quality nitride and high quality nitride are formed on the semiconductor structure. The high quality nitride in the NFET portion is damaged by ion implantation to facilitate its removal. A faceted epitaxial silicon RSD is formed on the ETSOI adjacent to the high quality nitride in the NFET portion. The high quality nitride in the PFET portion is damaged by ion implantation to facilitate its removal. Extensions are ion implanted into the ETSOI underneath the gate structure in the NFET portion.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: October 1, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Bala S. Haran, Pranita Kulkarni, Nicolas Loubet, Amlan Majumdar, Stefan Schmitz
  • Publication number: 20110163449
    Abstract: In accordance with one aspect of the invention, a method is provided for fabricating a semiconductor element having a contact via. In such method, a hole can be formed in a dielectric layer to at least partially expose a region including at least one of semiconductor or conductive material. A seed layer can be deposited over a major surface of the dielectric layer and over a surface within the hole. In one embodiment, the seed layer can include a metal selected from the group consisting of iridium, osmium, palladium, platinum, rhodium, and ruthenium. A layer consisting essentially of cobalt can be electroplated over the seed layer within the hole to form a contact via in electrically conductive communication with the region.
    Type: Application
    Filed: January 7, 2010
    Publication date: July 7, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James J. Kelly, Veeraghavan S. Basker, Bala S. Haran, Soon-Cheon Seo, Tuan A. Vo