Patents by Inventor Ban-Li Wu

Ban-Li Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210280511
    Abstract: A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.
    Type: Application
    Filed: May 10, 2021
    Publication date: September 9, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Tsung-Hsien Chiang, Yu-Chih Huang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Publication number: 20210272941
    Abstract: A package structure including a first redistribution layer, a semiconductor die, through insulator vias, an insulating encapsulant and a second redistribution layer. The first redistribution layer includes a dielectric layer, a conductive layer, and connecting portions electrically connected to the conductive layer. The dielectric layer has first and second surfaces, the connecting portions has a first side, a second side, and sidewalls joining the first side to the second side. The first side of the connecting portions is exposed from and coplanar with the first surface of the dielectric layer. The semiconductor die is disposed on the second surface of the dielectric layer. The through insulator vias are connected to the conductive layer. The insulating encapsulant is disposed on the dielectric layer and encapsulating the semiconductor die and the through insulator vias. The second redistribution layer is disposed on the semiconductor die and over the insulating encapsulant.
    Type: Application
    Filed: May 17, 2021
    Publication date: September 2, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo, Ban-Li Wu, Ying-Cheng Tseng, Chi-Hui Lai
  • Patent number: 11049850
    Abstract: A semiconductor package includes a semiconductor device including a first UBM structure, wherein the first UBM structure includes multiple first conductive strips, the first conductive strips extending in a first direction, multiple second conductive strips separated from and interleaved with the multiple first conductive strips, the second conductive strips extending in the first direction, wherein the multiple first conductive strips are offset in the first direction from the multiple second conductive strips by a first offset distance, and a substrate including a second UBM structure, the second UBM structure including multiple third conductive strips, each one of the multiple third conductive strips bonded to one of the multiple first conductive strips or one of the multiple second conductive strips.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: June 29, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Chi-Hui Lai, Ying-Cheng Tseng, Ban-Li Wu, Ting-Ting Kuo, Yu-Chih Huang, Chiahung Liu, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 11011501
    Abstract: A package structure including a first redistribution layer, a semiconductor die, through insulator vias, an insulating encapsulant and a second redistribution layer. The first redistribution layer includes a dielectric layer, a conductive layer, and connecting portions electrically connected to the conductive layer. The dielectric layer has first and second surfaces, the connecting portions has a first side, a second side, and sidewalls joining the first side to the second side. The first side of the connecting portions is exposed from and coplanar with the first surface of the dielectric layer. The semiconductor die is disposed on the second surface of the dielectric layer. The through insulator vias are connected to the conductive layer. The insulating encapsulant is disposed on the dielectric layer and encapsulating the semiconductor die and the through insulator vias. The second redistribution layer is disposed on the semiconductor die and over the insulating encapsulant.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: May 18, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo, Ban-Li Wu, Ying-Cheng Tseng, Chi-Hui Lai
  • Patent number: 11004786
    Abstract: A package structure includes a die, a TIV, a first encapsulant, a RDL structure, a thermal dissipation structure and a second encapsulant. The die has a first surface and a second surface opposite to each other. The TIV is laterally aside the die. The first encapsulant encapsulates sidewalls of the die and sidewalls of the TIV. The RDL structure is disposed on the first surface of the die and on the first encapsulant, electrically connected to the die and the TIV. The thermal dissipation structure is disposed over the second surface of die and electrically connected to the die through the TIV and the RDL structure. The second encapsulant encapsulates sidewalls of the thermal dissipation structure.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Tsung-Hsien Chiang, Yu-Chih Huang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Publication number: 20210098636
    Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.
    Type: Application
    Filed: January 20, 2020
    Publication date: April 1, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chih-Hao Chang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Publication number: 20210091065
    Abstract: A semiconductor device includes passive electrical components in a substrate; and an interconnect structure over the passive electrical components, conductive features of the interconnect structure being electrically coupled to the passive electrical components. The conductive features of the interconnect structure includes a first conductive line over the substrate; a conductive bump over the first conductive line, where in a plan view, the conductive bumps has a first elongated shape and is entirely disposed within boundaries of the first conductive line; and a first via between the first conductive line and the conductive bump, the first via electrically connected to the first conductive line and the conductive bump, where in the plan view, the first via has a second elongated shape and is entirely disposed within boundaries of the conductive bump.
    Type: Application
    Filed: December 7, 2020
    Publication date: March 25, 2021
    Inventors: Ying-Cheng Tseng, Yu-Chih Huang, Chih-Hsuan Tai, Ting-Ting Kuo, Chi-Hui Lai, Ban-Li Wu, Chiahung Liu, Hao-Yi Tsai
  • Publication number: 20210074694
    Abstract: A semiconductor package includes an integrated passive device (IPD) including one or more passive devices over a first substrate; and metallization layers over and electrically coupled to the one or more passive devices, where a topmost metallization layer of the metallization layers includes a first plurality of conductive patterns; and a second plurality of conductive patterns interleaved with the first plurality of conductive patterns. The IPD also includes a first under bump metallization (UBM) structure over the topmost metallization layer, where the first UBM structure includes a first plurality of conductive strips, each of the first plurality of conductive strips electrically coupled to a respective one of the first plurality of conductive patterns; and a second plurality of conductive strips interleaved with the first plurality of conductive strips, each of the second plurality of conductive strips electrically coupled to a respective one of the second plurality of conductive patterns.
    Type: Application
    Filed: November 16, 2020
    Publication date: March 11, 2021
    Inventors: Yu-Chih Huang, Chi-Hui Lai, Ban-Li Wu, Ying-Cheng Tseng, Ting-Ting Kuo, Chih-Hsuan Tai, Hao-Yi Tsai, Chuei-Tang Wang, Chung-Shi Liu, Chen-Hua Yu, Chiahung Liu
  • Publication number: 20210057302
    Abstract: In an embodiment, a device includes: a sensor die having a first surface and a second surface opposite the first surface, the sensor die having an input/output region and a first sensing region at the first surface; an encapsulant at least laterally encapsulating the sensor die; a conductive via extending through the encapsulant; and a front-side redistribution structure on the first surface of the sensor die, the front-side redistribution structure being connected to the conductive via and the sensor die, the front-side redistribution structure covering the input/output region of the sensor die, the front-side redistribution structure having a first opening exposing the first sensing region of the sensor die.
    Type: Application
    Filed: November 9, 2020
    Publication date: February 25, 2021
    Inventors: Tsung-Hsien Chiang, Yu-Chih Huang, Ting-Ting Kuo, Chih-Hsuan Tai, Ban-Li Wu, Ying-Cheng Tseng, Chi-Hui Lai, Chiahung Liu, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 10861841
    Abstract: A semiconductor device includes passive electrical components in a substrate; and an interconnect structure over the passive electrical components, conductive features of the interconnect structure being electrically coupled to the passive electrical components. The conductive features of the interconnect structure includes a first conductive line over the substrate; a conductive bump over the first conductive line, where in a plan view, the conductive bumps has a first elongated shape and is entirely disposed within boundaries of the first conductive line; and a first via between the first conductive line and the conductive bump, the first via electrically connected to the first conductive line and the conductive bump, where in the plan view, the first via has a second elongated shape and is entirely disposed within boundaries of the conductive bump.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ying-Cheng Tseng, Yu-Chih Huang, Chih-Hsuan Tai, Ting-Ting Kuo, Chi-Hui Lai, Ban-Li Wu, Chiahung Liu, Hao-Yi Tsai
  • Patent number: 10840227
    Abstract: A semiconductor package includes an integrated passive device (IPD) including one or more passive devices over a first substrate; and metallization layers over and electrically coupled to the one or more passive devices, where a topmost metallization layer of the metallization layers includes a first plurality of conductive patterns; and a second plurality of conductive patterns interleaved with the first plurality of conductive patterns. The IPD also includes a first under bump metallization (UBM) structure over the topmost metallization layer, where the first UBM structure includes a first plurality of conductive strips, each of the first plurality of conductive strips electrically coupled to a respective one of the first plurality of conductive patterns; and a second plurality of conductive strips interleaved with the first plurality of conductive strips, each of the second plurality of conductive strips electrically coupled to a respective one of the second plurality of conductive patterns.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chih Huang, Chi-Hui Lai, Ban-Li Wu, Ying-Cheng Tseng, Ting-Ting Kuo, Chih-Hsuan Tai, Hao-Yi Tsai, Chuei-Tang Wang, Chung-Shi Liu, Chen-Hua Yu, Chiahung Liu
  • Patent number: 10832985
    Abstract: In an embodiment, a device includes: a sensor die having a first surface and a second surface opposite the first surface, the sensor die having an input/output region and a first sensing region at the first surface; an encapsulant at least laterally encapsulating the sensor die; a conductive via extending through the encapsulant; and a front-side redistribution structure on the first surface of the sensor die, the front-side redistribution structure being connected to the conductive via and the sensor die, the front-side redistribution structure covering the input/output region of the sensor die, the front-side redistribution structure having a first opening exposing the first sensing region of the sensor die.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: November 10, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Hsien Chiang, Yu-Chih Huang, Ting-Ting Kuo, Chih-Hsuan Tai, Ban-Li Wu, Ying-Cheng Tseng, Chi-Hui Lai, Chiahung Liu, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20200294912
    Abstract: A package structure includes a die, a TIV, a first encapsulant, a RDL structure, a thermal dissipation structure and a second encapsulant. The die has a first surface and a second surface opposite to each other. The TIV is laterally aside the die. The first encapsulant encapsulates sidewalls of the die and sidewalls of the TIV. The RDL structure is disposed on the first surface of the die and on the first encapsulant, electrically connected to the die and the TIV. The thermal dissipation structure is disposed over the second surface of die and electrically connected to the die through the TIV and the RDL structure. The second encapsulant encapsulates sidewalls of the thermal dissipation structure.
    Type: Application
    Filed: March 15, 2019
    Publication date: September 17, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Tsung-Hsien Chiang, Yu-Chih Huang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Publication number: 20200279837
    Abstract: A semiconductor package includes a semiconductor device including a first UBM structure, wherein the first UBM structure includes multiple first conductive strips, the first conductive strips extending in a first direction, multiple second conductive strips separated from and interleaved with the multiple first conductive strips, the second conductive strips extending in the first direction, wherein the multiple first conductive strips are offset in the first direction from the multiple second conductive strips by a first offset distance, and a substrate including a second UBM structure, the second UBM structure including multiple third conductive strips, each one of the multiple third conductive strips bonded to one of the multiple first conductive strips or one of the multiple second conductive strips.
    Type: Application
    Filed: May 18, 2020
    Publication date: September 3, 2020
    Inventors: Chih-Hsuan Tai, Chi-Hui Lai, Ying-Cheng Tseng, Ban-Li Wu, Ting-Ting Kuo, Yu-Chih Huang, Chiahung Liu, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 10658348
    Abstract: A semiconductor package includes a semiconductor device including a first UBM structure, wherein the first UBM structure includes multiple first conductive strips, the first conductive strips extending in a first direction, multiple second conductive strips separated from and interleaved with the multiple first conductive strips, the second conductive strips extending in the first direction, wherein the multiple first conductive strips are offset in the first direction from the multiple second conductive strips by a first offset distance, and a substrate including a second UBM structure, the second UBM structure including multiple third conductive strips, each one of the multiple third conductive strips bonded to one of the multiple first conductive strips or one of the multiple second conductive strips.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Chi-Hui Lai, Ying-Cheng Tseng, Ban-Li Wu, Ting-Ting Kuo, Yu-Chih Huang, Chiahung Liu, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20200105738
    Abstract: A semiconductor device includes passive electrical components in a substrate; and an interconnect structure over the passive electrical components, conductive features of the interconnect structure being electrically coupled to the passive electrical components. The conductive features of the interconnect structure includes a first conductive line over the substrate; a conductive bump over the first conductive line, where in a plan view, the conductive bumps has a first elongated shape and is entirely disposed within boundaries of the first conductive line; and a first via between the first conductive line and the conductive bump, the first via electrically connected to the first conductive line and the conductive bump, where in the plan view, the first via has a second elongated shape and is entirely disposed within boundaries of the conductive bump.
    Type: Application
    Filed: December 10, 2018
    Publication date: April 2, 2020
    Inventors: Ying-Cheng Tseng, Yu-Chih Huang, Chih-Hsuan Tai, Ting-Ting Kuo, Chi-Hui Lai, Ban-Li Wu, Chiahung Liu, Hao-Yi Tsai
  • Publication number: 20200105638
    Abstract: In an embodiment, a device includes: a sensor die having a first surface and a second surface opposite the first surface, the sensor die having an input/output region and a first sensing region at the first surface; an encapsulant at least laterally encapsulating the sensor die; a conductive via extending through the encapsulant; and a front-side redistribution structure on the first surface of the sensor die, the front-side redistribution structure being connected to the conductive via and the sensor die, the front-side redistribution structure covering the input/output region of the sensor die, the front-side redistribution structure having a first opening exposing the first sensing region of the sensor die.
    Type: Application
    Filed: February 4, 2019
    Publication date: April 2, 2020
    Inventors: Tsung-Hsien Chiang, Yu-Chih Huang, Ting-Ting Kuo, Chih-Hsuan Tai, Ban-Li Wu, Ying-Cheng Tseng, Chi-Hui Lai, Chiahung Liu, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20200105730
    Abstract: A semiconductor package includes a semiconductor device including a first UBM structure, wherein the first UBM structure includes multiple first conductive strips, the first conductive strips extending in a first direction, multiple second conductive strips separated from and interleaved with the multiple first conductive strips, the second conductive strips extending in the first direction, wherein the multiple first conductive strips are offset in the first direction from the multiple second conductive strips by a first offset distance, and a substrate including a second UBM structure, the second UBM structure including multiple third conductive strips, each one of the multiple third conductive strips bonded to one of the multiple first conductive strips or one of the multiple second conductive strips.
    Type: Application
    Filed: December 10, 2018
    Publication date: April 2, 2020
    Inventors: Chih-Hsuan Tai, Chi-Hui Lai, Ying-Cheng Tseng, Ban-Li Wu, Ting-Ting Kuo, Yu-Chih Huang, Chiahung Liu, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20200058626
    Abstract: A package structure including a first redistribution layer, a semiconductor die, through insulator vias, an insulating encapsulant and a second redistribution layer. The first redistribution layer includes a dielectric layer, a conductive layer, and connecting portions electrically connected to the conductive layer. The dielectric layer has first and second surfaces, the connecting portions has a first side, a second side, and sidewalls joining the first side to the second side. The first side of the connecting portions is exposed from and coplanar with the first surface of the dielectric layer. The semiconductor die is disposed on the second surface of the dielectric layer. The through insulator vias are connected to the conductive layer. The insulating encapsulant is disposed on the dielectric layer and encapsulating the semiconductor die and the through insulator vias. The second redistribution layer is disposed on the semiconductor die and over the insulating encapsulant.
    Type: Application
    Filed: August 14, 2018
    Publication date: February 20, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo, Ban-Li Wu, Ying-Cheng Tseng, Chi-Hui Lai
  • Publication number: 20190131287
    Abstract: A semiconductor package includes an integrated passive device (IPD) including one or more passive devices over a first substrate; and metallization layers over and electrically coupled to the one or more passive devices, where a topmost metallization layer of the metallization layers includes a first plurality of conductive patterns; and a second plurality of conductive patterns interleaved with the first plurality of conductive patterns. The IPD also includes a first under bump metallization (UBM) structure over the topmost metallization layer, where the first UBM structure includes a first plurality of conductive strips, each of the first plurality of conductive strips electrically coupled to a respective one of the first plurality of conductive patterns; and a second plurality of conductive strips interleaved with the first plurality of conductive strips, each of the second plurality of conductive strips electrically coupled to a respective one of the second plurality of conductive patterns.
    Type: Application
    Filed: September 12, 2018
    Publication date: May 2, 2019
    Inventors: Yu-Chih Huang, Chi-Hui Lai, Ban-Li Wu, Ying-Cheng Tseng, Ting-Ting Kuo, Chih-Hsuan Tai, Hao-Yi Tsai, Chuei-Tang Wang, Chung-Shi Liu, Chen-Hua Yu, Chiahung Liu