Patents by Inventor Banu Meenakshi Nagasundaram

Banu Meenakshi Nagasundaram has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190303159
    Abstract: Disclosed embodiments relate to an instruction set architecture to facilitate energy-efficient computing for exascale architectures. In one embodiment, a processor includes a plurality of accelerator cores, each having a corresponding instruction set architecture (ISA); a fetch circuit to fetch one or more instructions specifying one of the accelerator cores, a decode circuit to decode the one or more fetched instructions, and an issue circuit to translate the one or more decoded instructions into the ISA corresponding to the specified accelerator core, collate the one or more translated instructions into an instruction packet, and issue the instruction packet to the specified accelerator core; and, wherein the plurality of accelerator cores comprise a memory engine (MENG), a collective engine (CENG), a queue engine (QENG), and a chain management unit (CMU).
    Type: Application
    Filed: March 29, 2018
    Publication date: October 3, 2019
    Inventors: Joshua B. FRYMAN, Jason M. HOWARD, Priyanka SURESH, Banu Meenakshi NAGASUNDARAM, Srikanth DAKSHINAMOORTHY, Ankit MORE, Robert PAWLOWSKI, Samkit JAIN, Pranav YEOLEKAR, Avinash M. SEEGEHALLI, Surhud KHARE, Dinesh SOMASEKHAR, David S. DUNNING, Romain E. Cledat, William Paul GRIFFIN, Bhavitavya B. BHADVIYA, Ivan B. GANEV
  • Patent number: 10296338
    Abstract: In one embodiment, a processor includes: an accelerator associated with a first address space; a core associated with a second address space and including an alternate address space configuration register to store configuration information to enable the core to execute instructions from the first address space; and a control logic to configure the core based in part on information in the alternate address space configuration register. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Brent R. Boswell, Banu Meenakshi Nagasundaram, Michael D. Abbott, Srikanth Dakshinamoorthy, Jason M. Howard, Joshua B. Fryman
  • Publication number: 20180165203
    Abstract: In one embodiment, a processor includes: an accelerator associated with a first address space; a core associated with a second address space and including an alternate address space configuration register to store configuration information to enable the core to execute instructions from the first address space; and a control logic to configure the core based in part on information in the alternate address space configuration register. Other embodiments are described and claimed.
    Type: Application
    Filed: December 9, 2016
    Publication date: June 14, 2018
    Inventors: Brent R. Boswell, Banu Meenakshi Nagasundaram, Michael D. Abbott, Srikanth Dakshinamoorthy, Jason M. Howard, Joshua B. Fryman