Patents by Inventor Baofu Zhu
Baofu Zhu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210043766Abstract: A laterally diffused metal-oxide semiconductor (LDMOS) device is disclosed. The LDMOS FET includes a gate structure between a source region and a drain region over a p-type semiconductor substrate; and a trench isolation partially under the gate structure and between the gate structure and the drain region. A p-well is under and adjacent the source region; and an n-well is under and adjacent the drain region. A counter doping region abuts and is between the p-well and the n-well, and is directly underneath the gate structure. The counter doping region increases drain-source breakdown voltage compares to conventional approaches.Type: ApplicationFiled: August 7, 2019Publication date: February 11, 2021Inventors: Baofu Zhu, Shesh Mani Pandey, Jiehui Shu, Sipeng Gu, Haiting Wang
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Patent number: 10910276Abstract: A structure, an STI structure and a related method are disclosed. The structure may include an active region extending from a substrate; a gate extending over the active region; and a source/drain region in the active region, and an STI structure. The STI structure includes a liner and a fill layer on the liner along the opposed longitudinal sides of a lower portion of the active region, and the fill layer along the opposed ends of the active region. The liner may include a tensile stress-inducing liner that imparts a transverse-to-length tensile stress in at least a lower portion of the active region but not lengthwise. The liner can be applied in an n-FET region and/or a p-FET region to improve performance.Type: GrantFiled: October 1, 2019Date of Patent: February 2, 2021Assignee: GLOBALFOUNDRIES INC.Inventors: Yongjun Shi, Xinyuan Dou, Chun Yu Wong, Hongliang Shen, Baofu Zhu
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Publication number: 20200411638Abstract: The present disclosure relates to semiconductor structures and, more particularly, to n-well resistors and methods of manufacture. The structure includes: a substrate composed of a N-well implant region and a deep N-well implant region; and a plurality of shallow trench isolation regions extending into both the N-well implant region and a deep N-well implant region.Type: ApplicationFiled: June 25, 2019Publication date: December 31, 2020Inventors: Shesh Mani PANDEY, Chung Foong TAN, Baofu ZHU
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Patent number: 10164099Abstract: One illustrative device disclosed herein includes, among other things, a fin defined on a substrate. A gate electrode structure is positioned above the fin in a channel region. A source/drain region is defined in the fin. The source/drain region includes a first epitaxial semiconductor material. The first epitaxial semiconductor material includes a dopant species having a first concentration. A diffusion blocking layer is positioned above the first epitaxial semiconductor material. A second epitaxial semiconductor material is positioned above the diffusion blocking layer. The second epitaxial semiconductor material includes the dopant species having a second concentration greater than the first concentration.Type: GrantFiled: February 6, 2018Date of Patent: December 25, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Shesh Mani Pandey, Pei Zhao, Baofu Zhu, Francis L. Benistant
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Publication number: 20180233415Abstract: A method for producing a finFET having a fin with thinned sidewalls on a lower portion above a shallow trench isolation (STI) regions is provided. Embodiments include forming a fin surrounded by STI regions on a substrate; recessing the STI regions, revealing an upper portion of the fin; forming a spacer over side and upper surfaces of the upper portion of the fin; recessing the STI regions, exposing a lower portion of the fin; and thinning sidewalls of the lower portion of the fin.Type: ApplicationFiled: April 6, 2018Publication date: August 16, 2018Inventors: Shesh Mani PANDEY, Baofu ZHU, Srikanth Balaji SAMAVEDAM
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Patent number: 10020386Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high-voltage, analog bipolar devices and methods of manufacture. The structure includes: a base region formed in a substrate; a collector region formed in the substrate and comprising a deep n-well region and an n-well region; and an emitter region formed in the substrate and comprising a deep n-well region and an n-well region.Type: GrantFiled: March 9, 2017Date of Patent: July 10, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Jagar Singh, Baofu Zhu
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Publication number: 20180175198Abstract: One illustrative device disclosed herein includes, among other things, a fin defined on a substrate. A gate electrode structure is positioned above the fin in a channel region. A source/drain region is defined in the fin. The source/drain region includes a first epitaxial semiconductor material. The first epitaxial semiconductor material includes a dopant species having a first concentration. A diffusion blocking layer is positioned above the first epitaxial semiconductor material. A second epitaxial semiconductor material is positioned above the diffusion blocking layer. The second epitaxial semiconductor material includes the dopant species having a second concentration greater than the first concentration.Type: ApplicationFiled: February 6, 2018Publication date: June 21, 2018Inventors: Shesh Mani Pandey, Pei Zhao, Baofu Zhu, Francis L. Benistant
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Patent number: 10002793Abstract: A gap fill method for sub-fin doping includes forming semiconductor fin arrays over a semiconductor substrate, forming a first dopant source layer over a first fin array and filling intra fin gaps within the first array, and forming a second dopant source layer over a second fin array and filling intra fin gaps within the second array. The first and second dopant source layers are recessed to expose a channel region of the fins. Thereafter, an annealing step is used to drive dopants from the dopant source layers locally into sub-fin regions of the fins below the channel regions.Type: GrantFiled: March 21, 2017Date of Patent: June 19, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Jiehui Shu, David P. Brunco, Jinping Liu, Baofu Zhu, Shesh Mani Pandey
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Patent number: 9966313Abstract: A method for producing a finFET having a fin with thinned sidewalls on a lower portion above a shallow trench isolation (STI) regions is provided. Embodiments include forming a fin surrounded by STI regions on a substrate; recessing the STI regions, revealing an upper portion of the fin; forming a spacer over side and upper surfaces of the upper portion of the fin; recessing the STI regions, exposing a lower portion of the fin; and thinning sidewalls of the lower portion of the fin.Type: GrantFiled: August 5, 2016Date of Patent: May 8, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Shesh Mani Pandey, Baofu Zhu, Srikanth Balaji Samavedam
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Publication number: 20180108732Abstract: The present disclosure relates to semiconductor structures and, more particularly, to notched fin structures and methods of manufacture. The structure includes: a fin structure composed of a substrate material and a stack of multiple epitaxially grown materials on the substrate material; a notch formed in a first epitaxially grown material of the stack of multiple epitaxially grown materials of the fin structure; an insulator material within the notch of the fin structure; and an insulator layer surrounding the fin structure and above a surface of the notch.Type: ApplicationFiled: October 13, 2016Publication date: April 19, 2018Inventors: Jiehui Shu, Baofu Zhu, Haifeng Sheng, Jinping Liu, Shesh Mani Pandey, Jagar Singh
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Patent number: 9947788Abstract: A method includes forming a gate electrode structure above a channel region defined in a semiconductor material. The semiconductor material is recessed in a source/drain region. A first material is epitaxially grown in the source/drain region. The first material includes a dopant species having a first concentration. A diffusion blocking layer is formed in the source/drain region above the first material. A second material is epitaxially grown in the source/drain region above the diffusion blocking layer. The second material comprises the dopant species having a second concentration greater than the first concentration.Type: GrantFiled: February 9, 2016Date of Patent: April 17, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Shesh Mani Pandey, Pei Zhao, Baofu Zhu, Francis L. Benistant
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Publication number: 20180040516Abstract: A method for producing a finFET having a fin with thinned sidewalls on a lower portion above a shallow trench isolation (STI) regions is provided. Embodiments include forming a fin surrounded by STI regions on a substrate; recessing the STI regions, revealing an upper portion of the fin; forming a spacer over side and upper surfaces of the upper portion of the fin; recessing the STI regions, exposing a lower portion of the fin; and thinning sidewalls of the lower portion of the fin.Type: ApplicationFiled: August 5, 2016Publication date: February 8, 2018Inventors: Shesh Mani PANDEY, Baofu ZHU, Srikanth Balaji SAMAVEDAM
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Publication number: 20170309623Abstract: We disclose semiconductor devices, comprising a semiconductor substrate comprising bulk silicon; and a plurality of fins formed on the semiconductor substrate; wherein each of the plurality of fins comprises a lower portion disposed on the semiconductor substrate and having a first width, and an upper portion disposed on the lower portion and having a second width, wherein the second width is greater than the first width, as well as methods, apparatus, and systems for fabricating such semiconductor devices.Type: ApplicationFiled: April 21, 2016Publication date: October 26, 2017Applicant: GLOBALFOUNDRIES INC.Inventors: Shesh Mani Pandey, Baofu Zhu
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Publication number: 20170288041Abstract: A method includes forming a fin in a semiconductor substrate. An isolation structure is formed adjacent the fin. A first portion of the fin extends above the isolation structure. A gate electrode is formed above the first portion of the fin. A fin spacer is formed on the first portion of the fin. The fin spacer covers less than 50% of a height of the first portion of the fin. An implantation process is performed in the presence of the fin spacer to form a doped region in the first portion of the fin.Type: ApplicationFiled: April 5, 2016Publication date: October 5, 2017Inventors: Shesh Mani Pandey, Baofu Zhu, Francis Benistant
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Publication number: 20170229578Abstract: A method includes forming a gate electrode structure above a channel region defined in a semiconductor material. The semiconductor material is recessed in a source/drain region. A first material is epitaxially grown in the source/drain region. The first material includes a dopant species having a first concentration. A diffusion blocking layer is formed in the source/drain region above the first material. A second material is epitaxially grown in the source/drain region above the diffusion blocking layer. The second material comprises the dopant species having a second concentration greater than the first concentration.Type: ApplicationFiled: February 9, 2016Publication date: August 10, 2017Inventors: Shesh Mani Pandey, Pei Zhao, Baofu Zhu, Francis L. Benistant
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Patent number: 9099434Abstract: A method of forming a device is disclosed. The method includes providing a substrate having a device region. The device region includes a source region, a gate region and a drain region defined thereon. The substrate is prepared with gate layers on the substrate. The gate layers are patterned to form a gate in the gate region and a field structure surrounding the drain region. A source and a drain are formed in the source region and drain region respectively. The drain is separated from the gate on a second side of the gate and the source is adjacent to a first side of the gate. An interconnection to the field structure is formed. The interconnection is coupled to a potential which distributes the electric field across the substrate between the second side of the gate and the drain.Type: GrantFiled: July 25, 2014Date of Patent: August 4, 2015Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Guowei Zhang, Purakh Raj Verma, Baofu Zhu
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Publication number: 20140332884Abstract: A method of forming a device is disclosed. The method includes providing a substrate having a device region. The device region includes a source region, a gate region and a drain region defined thereon. The substrate is prepared with gate layers on the substrate. The gate layers are patterned to form a gate in the gate region and a field structure surrounding the drain region. A source and a drain are formed in the source region and drain region respectively. The drain is separated from the gate on a second side of the gate and the source is adjacent to a first side of the gate. An interconnection to the field structure is formed. The interconnection is coupled to a potential which distributes the electric field across the substrate between the second side of the gate and the drain.Type: ApplicationFiled: July 25, 2014Publication date: November 13, 2014Inventors: Guowei ZHANG, Purakh Raj VERMA, Baofu ZHU
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Patent number: 8846464Abstract: An approach for controlling a critical dimension (CD) of a RMG of a semiconductor device is provided. Specifically, embodiments of the present invention allow for CD consistency between a dummy gate and a subsequent RMG. In a typical embodiment, a dummy gate having a cap layer is formed over a substrate. A re-oxide layer is then formed over the substrate and around the dummy gate. A set of doping implants will then be implanted in the substrate, and the re-oxide layer will subsequently be removed (after the set of doping implants have been implanted). A set of spacers will then be formed along a set of side walls of the dummy gate and an epitaxial layer will be formed around the set of side walls. Thereafter, the dummy gate will be replaced with a metal gate (e.g., an aluminum or tungsten body having a high-k metal liner there-around).Type: GrantFiled: March 13, 2013Date of Patent: September 30, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Bingwu Liu, Baofu Zhu, Nam Sung Kim
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Publication number: 20140273389Abstract: An approach for controlling a critical dimension (CD) of a RMG of a semiconductor device is provided. Specifically, embodiments of the present invention allow for CD consistency between a dummy gate and a subsequent RMG. In a typical embodiment, a dummy gate having a cap layer is formed over a substrate. A re-oxide layer is then formed over the substrate and around the dummy gate. A set of doping implants will then be implanted in the substrate, and the re-oxide layer will subsequently be removed (after the set of doping implants have been implanted). A set of spacers will then be formed along a set of side walls of the dummy gate and an epitaxial layer will be formed around the set of side walls. Thereafter, the dummy gate will be replaced with a metal gate (e.g., an aluminum or tungsten body having a high-k metal liner there-around).Type: ApplicationFiled: March 13, 2013Publication date: September 18, 2014Applicant: GLOBALFOUNDRIES INC.Inventors: Bingwu Liu, Baofu Zhu, Nam Sung Kim
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Patent number: 8790966Abstract: A method of forming a device is disclosed. The method includes providing a substrate having a device region. The device region includes a source region, a gate region and a drain region defined thereon. The substrate is prepared with gate layers on the substrate. The gate layers are patterned to form a gate in the gate region and a field structure surrounding the drain region. A source and a drain are formed in the source region and drain region respectively. The drain is separated from the gate on a second side of the gate and the source is adjacent to a first side of the gate. An interconnection to the field structure is formed. The interconnection is coupled to a potential which distributes the electric field across the substrate between the second side of the gate and the drain.Type: GrantFiled: October 18, 2011Date of Patent: July 29, 2014Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Guowei Zhang, Purakh Raj Verma, Baofu Zhu