Abstract: A process for preparing a porous ceramic body includes forming a green body with a mixture of ceramic material powder, binder material, and pore-forming particles. The process further includes extracting the binder material, decomposing the pore-forming particles, and removing residual organic materials from the green body at respective, progressively higher pre-firing temperatures. After these three stages, the green body is sintered at a still-higher temperature to form the porous ceramic body. Embodiments facilitate manufacturing and can render most or all surface grinding unnecessary, allowing electrode deposition directly onto substantially non-porous surfaces of the porous ceramic body that are naturally formed during sintering. Advantageously, the green body may be formed into net shape by injection molding the mixture that includes the pore-forming particles, and embodiments can result in porous ceramic bodies that are much thicker than currently available, with better structural integrity.

Abstract: A process for preparing a porous ceramic body includes forming a green body with a mixture of ceramic material powder, binder material, and pore-forming particles. The process further includes extracting the binder material, decomposing the pore-forming particles, and removing residual organic materials from the green body at respective, progressively higher pre-firing temperatures. After these three stages, the green body is sintered at a still-higher temperature to form the porous ceramic body. Embodiments facilitate manufacturing and can render most or all surface grinding unnecessary, allowing electrode deposition directly onto substantially non-porous surfaces of the porous ceramic body that are naturally formed during sintering. Advantageously, the green body may be formed into net shape by injection molding the mixture that includes the pore-forming particles, and embodiments can result in porous ceramic bodies that are much thicker than currently available, with better structural integrity.

Abstract: A low voltage current mirror termination circuit used with an ECL gate array for providing a constant output emitter follower reference current (Ief) which is independent of voltage variations in a separate output emitter follower power supply source (VEF) includes a lateral PNP transistor (Qp), an NPN mirror transistor (Qx), at least one pull-down transistor (Qf), and at least one NPN output emitter follower transistor (Qo). The current through the collector of the lateral PNP transistor (Qp) defines a mirror current (Ip). The base of the lateral transistor (Qp) is connected to receive a base bias voltage VEP. The current through the collector of the pull-down transistor (Qf) defines the constant output emitter follower reference current (Ief) which is proportional to the mirror current (Ip). The separate emitter follower power supply source (VEF) has a voltage which is lower than a supply source (VEE) so as to reduce significantly the power consumption.

Abstract: High emitter-coupled logic switching speeds and low standby power are achieved with a dual-port RAM cell in which two NPN Schottky transistors in a non-saturable bistable flip-flop configuration are flanked by a second pair of transistors whose collectors are individually coupled to the flip-flop collectors. The two output digit lines of the RAM are individually connected to the emitters of the flanking transistors, and their bases are individually coupled to the two select lines. A read signal on either select line enables a flanking transistor to sense the state of the RAM. Writing is accomplished by applying a high logic signal to both select lines and one digit line while the other digit line is dropped to a low state.

Abstract: A very high-speed exclusive OR/NOR circuit in which output function and its complement are propagated simultaneously. Developed particularly for use in integrated circuit applications, the basis circuit uses six NPN transistors in a tree configuration to select one of four mutually exclusive conductive paths which correspond to the four states of the truth table of a two-variable exclusive OR/NOR function.