Patents by Inventor Barry Joe Wolford
Barry Joe Wolford has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9262326Abstract: A memory system is disclosed. The memory system includes first and second memory devices, and a memory controller configured to selectively enable one of the memory devices, the memory controller having a first line coupled to the first and second memory devices and a second line coupled to the first and second memory devices. The first memory device is configured to provide a notification to the memory controller on the first line and the second memory device is configured to provide a notification to the memory controller on the second line. The first memory device is further configured not to load the first line and the second memory device is further configured not to load the second line when the memory controller is writing to the enabled memory device.Type: GrantFiled: November 30, 2006Date of Patent: February 16, 2016Assignee: QUALCOMM IncorporatedInventors: Barry Joe Wolford, James Edward Sullivan, Jr.
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Patent number: 8861410Abstract: A transaction request passes from an initiator through interconnect paths and a routing ID indicating the interconnect paths is prepended. A temporary ID is assigned to the routing ID, the transaction request with the temporary ID is sent to a target device, and a response having the temporary ID is received. The routing ID is retrieved using the target ID, and the response with the retrieved routing ID is sent to the initiator.Type: GrantFiled: October 31, 2011Date of Patent: October 14, 2014Assignee: QUALCOMM IncorporatedInventors: Jaya Prakash Subramaniam Ganasan, Prudhvi N. Nooney, Darren P. Umstead, Joseph L. Van Swearingen, Barry Joe Wolford, Mark Michael Schaffer
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Publication number: 20130107880Abstract: A transaction request passes from an initiator through interconnect paths and a routing ID indicating the interconnect paths is prepended. A temporary ID is assigned to the routing ID, the transaction request with the temporary ID is sent to a target device, and a response having the temporary ID is received. The routing ID is retrieved using the target ID, and the response with the retrieved routing ID is sent to the initiator.Type: ApplicationFiled: October 31, 2011Publication date: May 2, 2013Applicant: QUALCOMM INCORPORATEDInventors: Jaya Prakash Subramaniam Ganasan, Prudhvi N. Nooney, Darren P. Umstead, Joseph L. Van Swearingen, Barry Joe Wolford, Mark Michael Schaffer
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Patent number: 8077019Abstract: In a meeting or group event, people having a portable device, such as a cell phone or pager, may wish to be discretely notified when an important message is received, an urgent call comes in from a selected person or a selected group of people, or to be alerted to an upcoming important event without any audible alert to disturb the meeting or group event. To convey such a notification, a tactile alert is provided by vibrating the portable device according to a unique vibration pattern associated with the received communication. When a communication is received, a group identification (ID) is assigned based on the communication being a member of a classified group of source addresses. The portable device associates the group ID with a unique vibration pattern. To provide the alert, the portable device is vibrated according to the unique vibration pattern.Type: GrantFiled: October 27, 2006Date of Patent: December 13, 2011Assignee: QUALCOMM IncorporatedInventors: Richard Gerard Hofmann, Gerald Paul Michalak, Barry Joe Wolford
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Patent number: 7984202Abstract: Efficient techniques for controlling synchronization of bus transactions to improve performance and reduce power requirements in a shared memory system are described. Interconnect arrangements in complex processing systems are also described that provide efficient data transfers between bus masters and shared memory devices to improve performance and reduce power use. In one example, a method for controlling synchronization of bus transactions to remote devices is addressed. A device directed memory barrier command is received. The device directed memory barrier command is decoded to determine one or more destination devices. A memory barrier command is selectively routed to the one or more destination devices in response to the decoding. The described techniques combine high speed device directed memory barrier capability, improved bus bandwidth functionality, and power saving features.Type: GrantFiled: June 1, 2007Date of Patent: July 19, 2011Assignee: QUALCOMM IncorporatedInventors: Richard Gerard Hofmann, Jaya Prakash Ganasan, Barry Joe Wolford
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Publication number: 20110055495Abstract: Memory controller page management devices, systems, and methods are disclosed. In one embodiment, a memory controller is configured to access memory in response to a memory access request. The memory controller is configured to apply a page management policy to either leave open or close a memory page based on at least identification information of a requestor. In this manner, a memory page management policy can be applied by the memory controller to optimize memory access times and reduce latency based on the identification of the requestor. For example, the requestor may be associated with sequential or series of memory access requests to the same memory such that a leave open page management policy would be optimal for reduced memory access times. As another example, the requestor may be associated with memory access requests to random memory pages such that a close page management policy would be optimal for reduced memory access times.Type: ApplicationFiled: August 28, 2009Publication date: March 3, 2011Applicant: QUALCOMM INCORPORATEDInventors: Barry Joe Wolford, Perry Willmann Remaklus, JR.
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Patent number: 7783817Abstract: A weakly-ordered processing system implements an execution synchronization bus transaction, or “memory barrier” bus transaction, to enforce strongly-ordered data transfer bus transactions. A slave device that ensures global observability may “opt out” of the memory barrier protocol. In various embodiments, the opt-out decision may be made dynamically by each slave device asserting a signal, may be set system-wide during a Power-On Self Test (POST) by polling the slave devices and setting corresponding bits in a global observability register, or it may be hardwired by system designers so that only slave devices capable of performing out-of-order data transfer operations participate in the memory barrier protocol.Type: GrantFiled: August 31, 2006Date of Patent: August 24, 2010Assignee: QUALCOMM IncorporatedInventors: James Edward Sullivan, Jr., Barry Joe Wolford
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Publication number: 20100169527Abstract: An apparatus is described for data processing in a computer system. The apparatus comprises a data processing device having a data processing master, a functionally coupled data processor core, and a functionally coupled data processor slave. Both the data processing master and the data processing slave are coupled to a common bus or common crossbar switch. The data processing device processes the data associated with transfers to or from the data processor slave. System masters will direct transactions that require data processing to the data processing slave, which will indirectly interact with the target memory slave. System masters will direct transactions that do not require data processing, directly to the target memory slave.Type: ApplicationFiled: March 8, 2010Publication date: July 1, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bernard Charles Drerup, Richard Siegmund, JR., Barry Joe Wolford
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Patent number: 7707347Abstract: An apparatus is described for data processing in a computer system. The apparatus comprises a data processing device having a data processing master, a functionally coupled data processor core, and a functionally coupled data processor slave. Both the data processing master and the data processing slave are coupled to a common bus or common crossbar switch. The data processing device processes the data associated with transfers to or from the data processor slave. System masters will direct transactions that require data processing to the data processing slave, which will indirectly interact with the target memory slave. System masters will direct transactions that do not require data processing, directly to the target memory slave.Type: GrantFiled: January 14, 2009Date of Patent: April 27, 2010Assignee: International Business Machines CorporationInventors: Bernard Charles Drerup, Richard Siegmund, Jr., Barry Joe Wolford
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Method and apparatus for obtaining memory status information cross-reference to related applications
Patent number: 7620783Abstract: In one embodiment taught herein, a memory module selectively uses its write data mask input as a status output on which it provides status signaling to an associated memory controller. The memory module configures its data mask input as a status output at one or more times not conflicting with write operations. Correspondingly, the memory controller configures its write data mask output as a status input at such times, for receipt of status signaling from the memory module. In one embodiment, the memory module maintains a status register related to one or more operating conditions of the module, such as temperature, and signals status information changes to the memory controller by driving the module's data mask input. In response to such signaling, the memory controller initiates a read of the module's status register to obtain updated status information, and takes appropriate action, such as by changing the module's refresh rate.Type: GrantFiled: October 27, 2006Date of Patent: November 17, 2009Assignee: QUALCOMM IncorporatedInventors: Barry Joe Wolford, James Edward Sullivan, Jr. -
Patent number: 7593279Abstract: Status information comprising data not stored in a memory array is efficiently read from a plurality of parallel memory devices sharing an N-bit data bus by configuring each memory device to drive the status information on a different subset M of the N bits, and tri-state the remaining N-M bits. Each memory device is additionally configured to drive zero, one or more data strobes associated with the subset M, and tri-state the remaining data strobes. A memory controller may simultaneously read status information from two or more memory devices in parallel, with each memory device driving a separate subset M of the N-bit bus. Each memory device may serialize the status information, and drive it on the subset M of the bus in burst form. Each memory device may include a configuration register initialized by a memory controller to define its subset M.Type: GrantFiled: October 11, 2006Date of Patent: September 22, 2009Assignee: QUALCOMM IncorporatedInventors: Barry Joe Wolford, James Edward Sullivan, Jr.
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Patent number: 7590021Abstract: A DRAM or SDRAM component maintains an indicator that indicates whether or not an independently refreshable memory unit of a DRAM array, such as a row, contains valid data. When a refresh operation is directed to the associated memory, the refresh operation is suppressed if the memory does not contain valid data. Significant power savings may be realized by suppressing refresh operations directed to invalid data.Type: GrantFiled: July 26, 2007Date of Patent: September 15, 2009Assignee: QUALCOMM IncorporatedInventors: Gerald Paul Michalak, Barry Joe Wolford
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Publication number: 20090132743Abstract: An apparatus is described for data processing in a computer system. The apparatus comprises a data processing device having a data processing master, a functionally coupled data processor core, and a functionally coupled data processor slave. Both the data processing master and the data processing slave are coupled to a common bus or common crossbar switch. The data processing device processes the data associated with transfers to or from the data processor slave. System masters will direct transactions that require data processing to the data processing slave, which will indirectly interact with the target memory slave. System masters will direct transactions that do not require data processing, directly to the target memory slave.Type: ApplicationFiled: January 14, 2009Publication date: May 21, 2009Inventors: Bernard Charles Drerup, Richard Siegmund, JR., Barry Joe Wolford
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Patent number: 7526595Abstract: An apparatus and method is described for data processing in a computer system. The apparatus comprises a data processing device having a data processing master, a functionally coupled data processor core, and a functionally coupled data processor slave. Both the data processing master and the data processing slave are coupled to a common bus or common crossbar switch. The data processing device processes the data associated with transfers to or from the data processor slave. System masters will direct transactions that require data processing to the data processing slave, which will indirectly interact with the target memory slave. System masters will direct transactions that do not require data processing, directly to the target memory slave.Type: GrantFiled: July 25, 2002Date of Patent: April 28, 2009Assignee: International Business Machines CorporationInventors: Bernard Charles Drerup, Richard Siegmund, Jr., Barry Joe Wolford
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Patent number: 7490201Abstract: A method, and bus prefetching mechanism are provided for implementing enhanced buffer control. A computer system includes a plurality of masters and at least one slave exchanging data over a system bus and the slave prefetches read data under control of a master. The master generates a continue bus signal that indicates a new or a continued request. The master generates a prefetch bus signal that indicates an amount to prefetch including no prefetching. The master includes a mechanism for continuing a sequence of reads allowing prefetching until a request is made indicating a prefetch amount of zero.Type: GrantFiled: November 26, 2007Date of Patent: February 10, 2009Assignee: International Business Machines CorporationInventors: Bernard Charles Drerup, Richard Nicholas, Barry Joe Wolford
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Publication number: 20090027989Abstract: A DRAM or SDRAM component maintains an indicator that indicates whether or not an independently refreshable memory unit of a DRAM array, such as a row, contains valid data. When a refresh operation is directed to the associated memory, the refresh operation is suppressed if the memory does not contain valid data. Significant power savings may be realized by suppressing refresh operations directed to invalid data.Type: ApplicationFiled: July 26, 2007Publication date: January 29, 2009Applicant: QUALCOMM INCORPORATEDInventors: Gerald Paul Michalak, Barry Joe Wolford
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Publication number: 20080301342Abstract: Efficient techniques for controlling synchronization of bus transactions to improve performance and reduce power requirements in a shared memory system are described. Interconnect arrangements in complex processing systems are also described that provide efficient data transfers between bus masters and shared memory devices to improve performance and reduce power use. In one example, a method for controlling synchronization of bus transactions to remote devices is addressed. A device directed memory barrier command is received. The device directed memory barrier command is decoded to determine one or more destination devices. A memory barrier command is selectively routed to the one or more destination devices in response to the decoding. The described techniques combine high speed device directed memory barrier capability, improved bus bandwidth functionality, and power saving features.Type: ApplicationFiled: June 1, 2007Publication date: December 4, 2008Inventors: Richard Gerard Hofmann, Jaya Prakash Ganasan, Barry Joe Wolford
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Publication number: 20080089138Abstract: Status information comprising data not stored in a memory array is efficiently read from a plurality of parallel memory devices sharing an N-bit data bus by configuring each memory device to drive the status information on a different subset M of the N bits, and tri-state the remaining N-M bits. Each memory device is additionally configured to drive zero, one or more data strobes associated with the subset M, and tri-state the remaining data strobes. A memory controller may simultaneously read status information from two or more memory devices in parallel, with each memory device driving a separate subset M of the N-bit bus. Each memory device may serialize the status information, and drive it on the subset M of the bus in burst form. Each memory device may include a configuration register initialized by a memory controller to define its subset M.Type: ApplicationFiled: October 11, 2006Publication date: April 17, 2008Inventors: Barry Joe Wolford, James Edward Sullivan
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Publication number: 20080059683Abstract: A weakly-ordered processing system implements an execution synchronization bus transaction, or “memory barrier” bus transaction, to enforce strongly-ordered data transfer bus transactions. A slave device that ensures global observability may “opt out” of the memory barrier protocol. In various embodiments, the opt-out decision may be made dynamically by each slave device asserting a signal, may be set system-wide during a Power-On Self Test (POST) by polling the slave devices and setting corresponding bits in a global observability register, or it may be hardwired by system designers so that only slave devices capable of performing out-of-order data transfer operations participate in the memory barrier protocol.Type: ApplicationFiled: August 31, 2006Publication date: March 6, 2008Inventors: James Edward Sullivan, Barry Joe Wolford
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Publication number: 20080040559Abstract: A memory system is disclosed. The memory system includes first and second memory devices, and a memory controller configured to selectively enable one of the memory devices, the memory controller having a first line coupled to the first and second memory devices and a second line coupled to the first and second memory devices. The first memory device is configured to provide a notification to the memory controller on the first line and the second memory device is configured to provide a notification to the memory controller on the second line. The first memory device is further configured not to load the first line and the second memory device is further configured not to load the second line when the memory controller is writing to the enabled memory device.Type: ApplicationFiled: November 30, 2006Publication date: February 14, 2008Inventors: Barry Joe Wolford, James Edward Sullivan