Patents by Inventor Barry M. Trager

Barry M. Trager has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130003213
    Abstract: A method for longitudinal position (LPOS) detection in a magnetic tape storage system for storing data upon linear tape open (LTO) magnetic storage tape, which data includes odd and even 36-bit LPOS words with error correcting ability. The method includes first encoding positional information onto the tape within the 36-bit LPOS words using each LPOS word's 8-bit sync mark field, and six of each LPOS word's 4-bit symbol fields, wherein 6 of 24 total bits comprise the encoded 8-bit sync mark field: Sy, and six 4-bit symbol fields are utilized as parity bits. The magnetic tape storage system passes the LTO magnetic storage tape encoded with the odd and even LPOS words with error correcting ability longitudinally across a servo reader/writer at a known speed, decoding the encoded positional information and detecting and correcting both ambiguous bits and single erroneous bit errors.
    Type: Application
    Filed: September 12, 2012
    Publication date: January 3, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: William J. Kabelac, Barry M. Trager, Shmuel Winograd
  • Patent number: 8271857
    Abstract: The invention includes a method for longitudinal position (LPOS) detection in a magnetic tape storage system for storing data upon linear tape open (LTO) magnetic storage tape, which data includes odd and even 36-bit LPOS words with error correcting ability.
    Type: Grant
    Filed: May 13, 2008
    Date of Patent: September 18, 2012
    Assignee: International Business Machines Corporation
    Inventors: William J. Kabelac, Barry M. Trager, Shmuel Winograd
  • Publication number: 20120198309
    Abstract: Correcting memory device (chip) and memory channel failures in the presence of known memory device failures. A memory channel failure is located and corrected, or alternatively up to c chip failures are corrected and up to d chip failures are detected in the presence of up to u chips that are marked as suspect. A first stage of decoding is performed that results in recovering an estimate of correctable errors affecting the data or in declaring an uncorrectable error state. When an uncorrectable error state is declared, a second stage of decoding is performed to attempt to correct u erasures and a channel error in M iterations where the channel location is changed in each iteration. A correctable error is declared in response to exactly one of the M iterations being successful.
    Type: Application
    Filed: January 29, 2011
    Publication date: August 2, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Luiz C. Alves, Luis A. Lastras-Montano, Patrick J. Meaney, Eldee Stephens, Barry M. Trager
  • Patent number: 8185801
    Abstract: A system to improve error code decoding using historical information. An example system includes storage partitioned into memory ranks, and a table to record symbols having failures for each memory rank. The system generates a memory rank score for each memory rank. The system also includes an error control decoder that uses the memory rank score when each memory rank is accessed in order to determine whether an error should be corrected or not.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: May 22, 2012
    Assignee: International Business Machines Corporation
    Inventors: Timothy J. Dell, Luis A. Lastras-Montano, Barry M. Trager, Shmuel Winograd
  • Patent number: 8185800
    Abstract: A system to improve error control coding. An example system includes memory chips of at least two different kinds. The system also includes error control encoder circuitry to substantially encode data for storage in any memory rank. The system further includes error control decoder circuitry to substantially decode encoded data received from any memory rank. The error decoder circuitry is comprised of a slow decoder and a fast decoder.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: May 22, 2012
    Assignee: International Business Machines Corporation
    Inventors: Paul W. Coteus, Luis A. Lastras-Montano, Warren Edward Maule, Barry M. Trager, Shmuel Winograd
  • Patent number: 8181094
    Abstract: A system to improve error correction includes a fast decoder to process data packets until the fast decoder finds an uncorrectable error in a data packet at which point a request for at least two data packets is generated. The system also includes a slow decoder to correct the uncorrectable error in a data packet based upon the at least two data packets.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: May 15, 2012
    Assignee: International Business Machines Corporation
    Inventors: Luis A. Lastras-Montano, Piyush C. Patel, Eric E. Retter, Barry M. Trager, Michael R. Trombley, Shmuel Winograd, Kenneth L. Wright
  • Patent number: 8176391
    Abstract: A system to improve miscorrection rates in error control code may include an error control decoder with a safe decoding mode that processes at least two data packets. The system may also include a buffer to receive the processed at least two data packets from the error control decoder. The error control decoder may apply a logic OR operation to the uncorrectable error signal related to the processing of the at least two data packets to produce a global uncorrectable error signal. The system may further include a recipient to receive the at least two data packets and the global uncorrectable error signal.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: May 8, 2012
    Assignee: International Business Machines Corporation
    Inventors: Irving G. Baysah, Timothy J. Dell, Luis A. Lastras-Montano, Warren E. Maule, Eric E. Retter, Barry M. Trager, Michael R. Trombley, Shmuel Winograd, Kenneth L. Wright
  • Patent number: 8171377
    Abstract: A system to improve memory reliability in computer systems that may include memory chips, and may rely on a error control encoder to send codeword symbols for storage in each of the memory chips. At least two symbols from a codeword are assigned to each memory chip and therefore failure of any of the memory chips could affect two symbols or more. The system may also include a table to record failures and partial failures of the codeword symbols for each of the memory chips so the error control encoder can correct subsequent partial failures based upon the previous partial failures. The error control coder is capable of correcting and/or detecting more errors if only a fraction of a chip is noted in the table as having a failure as opposed to a full chip noted as having a failure.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: May 1, 2012
    Assignee: International Business Machines Corporation
    Inventors: Timothy J. Dell, Luis A. Lastras-Montano, Barry M. Trager, Shmuel Winograd
  • Publication number: 20120005561
    Abstract: An error correction method and system includes an Encoder and Syndrome-generator that operate in parallel to reduce the amount of circuitry used to compute check symbols and syndromes for error correcting codes. The system and method computes the contributions to the syndromes and check symbols 1 bit at a time instead of 1 symbol at a time. As a result, the even syndromes can be computed as powers of the odd syndromes. Further, the system assigns symbol addresses so that there are, for an example GF(28) which has 72 symbols, three (3) blocks of addresses which differ by a cube root of unity to allow the data symbols to be combined for reducing size and complexity of odd syndrome circuits. Further, the implementation circuit for generating check symbols is derived from syndrome circuit using the inverse of the part of the syndrome matrix for check locations.
    Type: Application
    Filed: June 24, 2011
    Publication date: January 5, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Barry M. Trager, Shmuel Winograd
  • Publication number: 20110320918
    Abstract: Error correction and detection in a redundant memory system including a a computer implemented method that includes receiving data including error correction code (ECC) bits, the receiving from a plurality of channels, each channel comprising a plurality of memory devices at memory device locations. The method also includes computing syndromes of the data; receiving a channel identifier of one of the channels; and removing a contribution of data received on the channel from the computed syndromes, the removing resulting in channel adjusted syndromes. The channel adjusted syndromes are decoded resulting in channel adjusted memory device locations of failing memory devices, the channel adjusted memory device locations corresponding to memory device locations.
    Type: Application
    Filed: June 24, 2010
    Publication date: December 29, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Luis C. Alves, Luis A. Lastras-Montano, Patrick J. Meaney, Eldee Stephens, Barry M. Trager
  • Publication number: 20110219208
    Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC).
    Type: Application
    Filed: January 10, 2011
    Publication date: September 8, 2011
    Applicant: International Business Machines Corporation
    Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Brian Smith, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
  • Patent number: 8010875
    Abstract: A method and system are disclosed for detecting memory chip failure in a computer memory system. The method comprises the steps of accessing user data from a set of user data chips, and testing the user data for errors using data from a set of system data chips. This testing is done by generating a sequence of check symbols from the user data, grouping the user data into a sequence of data symbols, and computing a specified sequence of syndromes. If all the syndromes are zero, the user data has no errors. If one of the syndromes is non-zero, then a set of discriminator expressions are computed, and used to determine whether a single or double symbol error has occurred. In the preferred embodiment, less than two full system data chips are used for testing and correcting the user data.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: August 30, 2011
    Assignee: International Business Machines Corporation
    Inventors: Alan G. Gara, Dong Chen, Paul W. Coteus, William T. Flynn, James A. Marcella, Todd Takken, Barry M. Trager, Shmuel Winograd
  • Publication number: 20100299576
    Abstract: A system to improve miscorrection rates in error control code may include an error control decoder with a safe decoding mode that processes at least two data packets. The system may also include a buffer to receive the processed at least two data packets from the error control decoder. The error control decoder may apply a logic OR operation to the uncorrectable error signal related to the processing of the at least two data packets to produce a global uncorrectable error signal. The system may further include a recipient to receive the at least two data packets and the global uncorrectable error signal.
    Type: Application
    Filed: January 31, 2008
    Publication date: November 25, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Irving G. Baysah, Timothy J. Dell, Luis A. Lastras-Montano, Warren E. Maule, Eric E. Retter, Barry M. Trager, Michael R. Trombley, Shmuel Winograd, Kenneth L. Wright
  • Publication number: 20100293436
    Abstract: A system to improve error control coding may include memory chips of at least two different kinds. The system may also include error control encoder circuitry to substantially encode data for storage in any memory rank. The system may further include error control decoder circuitry to substantially decode encoded data received from any memory rank. The error decoder circuitry is comprised of a slow decoder and a fast decoder.
    Type: Application
    Filed: January 31, 2008
    Publication date: November 18, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul W. Coteus, Luis A. Lastras-Montano, Warren Edward Maule, Barry M. Trager, Shmuel Winograd
  • Publication number: 20100293437
    Abstract: A system to improve memory failure management may include memory, and an error control decoder to determine failures in the memory. The system may also include an agent that may monitor failures in the memory. The system may further include a table where the error control decoder may record the failures, and where the agent can read and write to.
    Type: Application
    Filed: January 31, 2008
    Publication date: November 18, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Marc A. Gollub, Luis A. Lastras-Montano, Piyush C. Patel, Eric E. Retter, Barry M. Trager, Shmuel Winograd, Kenneth L. Wright
  • Publication number: 20100293438
    Abstract: A system to improve error correction may include a fast decoder to process data packets until the fast decoder finds an uncorrectable error in a data packet at which point a request for at least two data packets is generated. The system may also include a slow decoder to possibly correct the uncorrectable error in a data packet based upon the at least two data packets.
    Type: Application
    Filed: January 31, 2008
    Publication date: November 18, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Luis A. Lastras-Montano, Piyush C. Patel, Eric E. Retter, Barry M. Trager, Michael R. Trombley, Shmuel Winograd, Kenneth L. Wright
  • Publication number: 20100287436
    Abstract: A system to improve error code decoding with retries may include a processing unit that requests data packets, and a queue to hold the data packets for the processing unit. The system may also include a decoder to determine a processing time for each data packet in the queue based upon any errors in each data packet, and if the processing time for a particular data packet is greater than a threshold, then to renew any requests for the data packets that are in the queue.
    Type: Application
    Filed: January 31, 2008
    Publication date: November 11, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Luis A. Lastras-Montano, Piyush C. Patel, Eric E. Retter, Barry M. Trager, Michael R. Trombley, Shmuel Winogard
  • Publication number: 20100287454
    Abstract: A system to improve error code decoding using historical information may include storage partitioned into memory ranks, and a table to record symbols having failures for each memory rank. The system may also generate a memory rank score for each memory rank. The system may also include an error control decoder that may use the memory rank score when each memory rank is accessed in order to determine whether an error should be corrected or not.
    Type: Application
    Filed: January 31, 2008
    Publication date: November 11, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy J. Dell, Luis A. Lastras-Montano, Barry M. Trager, Shmuel Winograd
  • Publication number: 20100287445
    Abstract: A system to improve memory reliability in computer systems that may include memory chips, and may rely on a error control encoder to send codeword symbols for storage in each of the memory chips. At least two symbols from a codeword are assigned to each memory chip and therefore failure of any of the memory chips could affect two symbols or more. The system may also include a table to record failures and partial failures of the codeword symbols for each of the memory chips so the error control encoder can correct subsequent partial failures based upon the previous partial failures. The error control coder is capable of correcting and/or detecting more errors if only a fraction of a chip is noted in the table as having a failure as opposed to a full chip noted as having a failure.
    Type: Application
    Filed: January 31, 2008
    Publication date: November 11, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy J. Dell, Luis A. Lastras-Montano, Barry M. Trager, Shmuel Winograd
  • Publication number: 20090287982
    Abstract: The invention includes a method for longitudinal position (LPOS) detection in a magnetic tape storage system for storing data upon linear tape open (LTO) magnetic storage tape, which data includes odd and even 36-bit LPOS words with error correcting ability.
    Type: Application
    Filed: May 13, 2008
    Publication date: November 19, 2009
    Applicant: International Business Machines Corporation
    Inventors: William J. Kabelac, Barry M. Trager, Shmuel Winograd