Abstract: In various embodiments, the present disclosure includes a system for sending 50 gigabits per second (Gbps), 75 Gbps, and 100 Gbps at 50 gigabaud (GBaud) for passive optical networks (PON) downstream and upstream. The system allows for transmission of three data rates at a single baud-rate while only using 2-bits of information per sample. A motivation for sending three data rates at a single baud-rate is to allow for further granularity in the control of the data-rates for downstream and upstream traffic in a flexible PON system based on the link margin. For example, the system can use non-return-to-zero (NRZ) at 50 GBaud for 50 Gbps and can use four-level pulse-amplitude modulation (PAM-4) at 50 GBaud for 100 Gbps. In addition for 75 Gbps, a double square-8 (DSQ-8) constellation can be used at 50 GBaud.

Abstract: System and method of timing recovery to achieve sampling phase optimization with aid of equalization adaptation. For equalizer filter, the offset between a current Center of Filter (COF) value and a nominal COF value is used as a measure for a clock phase correction resulted from an adaptive equalization process. A COF may be defined as a function of two selected tap weights or equal to a selected tap weight. The nominal COF value can be dynamically adapted based on the real-time sampling phase error. The tap weights of the equalizer filter are adjusted to decrease the offset, e.g., by interpolating/extrapolating selected tap weights based on the offset. By using sampling phase error as a feedback for COF_nom updating and so for equalization adaptation, the clock delay correction contributed by the adaptive equalization process is advantageously controlled to benefit sampling phase optimization.

Abstract: A receiver capable of receive and process data signals of multiple baud rates by using an equalizer that is disposed upstream of a decimator. The receiver includes an equalizer coupled to an output of an analog-to-digital converter (ADC), and a decimator couple to the output of the equalizer. The ADC and the equalizer both operate in full rates even in the case of lower data rate, e.g., half or quarter data rate. As the equalizer inherently can inherent remove high frequency noise as well as perform equalization, it practically functions as a low pass filter (LPF). Thereby, there is no need to introduce an extra dedicate LPF upstream of the decimator. This can advantageously and significantly simplify circuitry design and reduce latency.

Abstract: A receiver including an equalizer disposed upstream of a decimator and capable of effectively preventing undesirable interaction between equalization adaptation and the overall timing recovery loop in cases of various data rates. The equalizer operates in a full operation rate even in the case of a lower-than-full data rate, e.g., half or quarter data rate. For input analog signal having 1/M of the full data rate (M>1), M or more Center of Filter (COF) values are determine. Each COF may be derived from a function of a respective set of tap weights and compared with a corresponding nominal COF to obtain a COF offset. The resultant COF offsets are used as indications of clock phase correction caused by equalization adaptation to adjust a set of selected tap weights. The taps selected for adjustment encompass at least M samples to correctly indicate the COF offset associate with one symbol.

Abstract: System and method of comparing-selecting state metric values for high speed Viterbi decoding. In an Add-Compare-Select (ACS) unit, a select control signal is produced by Boolean operations on comparator decision signals and used to control a multiplexer structure. The comparator decision signals can be generated in parallel by an array of comparators comparing all possible pairs of a set of state metrics values. The Boolean operations are predefined through Boolean algebra that uses the decision signals as variables and complies with restriction imposed by the selection criteria, e.g., to select an minimum or maximum value of the set of state metrics values. The Boolean operations are performed by a logic module implemented using basic logic gates, such as AND, OR and NOT. As a result, the multiplexer structure that receives the set of input values can output the optimum value responsive to the select control signal.

Abstract: System and method of comparing-selecting state metric values for high speed. Viterbi decoding. In an Add-Compare-Select (ACS) unit, a select-control signal is produced by Boolean operations on comparator decision signals and used to control a multiplexer structure. The comparator decision signals can be generated in parallel by an array of comparators comparing all possible pairs of a set of state metrics values. The Boolean operations are predefined through Boolean algebra that uses the decision signals as variables and complies with restriction imposed by the selection criteria, e.g., to select an minimum or maximum value of the set of state metrics values. The Boolean operations are performed by a logic module implemented using basic logic gates, such as AND, OR and NOT. As a result, the multiplexer structure that receives the set of input values can output the optimum value responsive to the select control signal.