Abstract: Some embodiments include an integrated assembly having a memory array over a base. First sense-amplifier-circuitry is associated with the base and includes sense amplifiers directly under the memory array. Vertically-extending digit lines are associated with the memory array and are coupled with the first sense-amplifier-circuitry. Second sense-amplifier-circuitry is associated with the base and is offset from the first sense-amplifier-circuitry. Control circuitry is configured to selectively couple the digit lines to either a voltage supply terminal or to the second sense-amplifier-circuitry.

Abstract: An apparatus may include a refresh control circuit with multiple timing circuits. The timing circuits may be used to control steal rates, e.g., the rate of refresh time slots dedicated to healing victim word lines of row hammers. The timing circuits may be controlled to allow independent adjustment of the steal rates for different victim word lines. Thus, different victim word lines may be refreshed at different rates and the different rates may be independent of one another.

Abstract: A method of forming a microelectronic device comprises forming a first microelectronic device structure comprising a first semiconductor structure, a first isolation material over the first semiconductor structure, and first conductive routing structures over the first semiconductor structure and surrounded by the first isolation material. A second microelectronic device structure comprising a second semiconductor structure and a second isolation material over the second semiconductor structure is formed. The second isolation material is bonded to the first isolation material to attach the second microelectronic device structure to the first microelectronic device structure. Memory cells comprising portions of the second semiconductor structure are formed after attaching the second microelectronic device structure to the first microelectronic device structure. Control logic devices including transistors comprising portions of the first semiconductor structure are formed after forming the memory cells.

Abstract: A multi-mode voltage pump may be configured to select an operational mode based on a temperature of a semiconductor device. The selected mode for a range of temperature values may be determined based on process variations and operational differences caused by temperature changes. The different selected modes of operation of the multi-mode voltage pump may provide pumped voltage having different voltage magnitudes. For example, the multi-mode voltage pump may operate in a first mode that uses two stages to provide a first VPP voltage, a second mode that uses a single stage to provide a second VPP voltage, or a third mode that uses a mixture of a single stage and two stages to provide a third VPP voltage. The third VPP voltage may be between the first and second VPP voltages, with the first VPP voltage having the greatest magnitude. Control signal timing of circuitry of the multi-mode voltage pump may be based on an oscillator signal.

Abstract: An apparatus may include a refresh control circuit with multiple timing circuits. The timing circuits may be used to control steal rates, e.g., the rate of refresh time slots dedicated to healing victim word lines of row hammers. The timing circuits may be controlled to allow independent adjustment of the steal rates for different victim word lines. Thus, different victim word lines may be refreshed at different rates and the different rates may be independent of one another.

Abstract: A method of forming a microelectronic device comprises forming a first microelectronic device structure comprising a first semiconductor structure, a first isolation material over the first semiconductor structure, and first conductive routing structures over the first semiconductor structure and surrounded by the first isolation material. A second microelectronic device structure comprising a second semiconductor structure and a second isolation material over the second semiconductor structure is formed. The second isolation material is bonded to the first isolation material to attach the second microelectronic device structure to the first microelectronic device structure. Memory cells comprising portions of the second semiconductor structure are formed after attaching the second microelectronic device structure to the first microelectronic device structure. Control logic devices including transistors comprising portions of the first semiconductor structure are formed after forming the memory cells.

Abstract: Fuse logic is configured to selectively enable certain group of fuses of a fuse array to support one of column (or row) redundancy in one application or error correction code (ECC) operations in another application. For example, the fuse logic may decode the group of fuses to enable a replacement column (or row) of memory cells in one mode or application, and decodes a subset of the group of fuses to retrieve ECC data corresponding to a second group of fuses are encoded to enable a different replacement column or row of memory cells in a second mode or application. The fuse logic includes an ECC decode logic circuit that is selectively enabled to detect and correct errors in data encoded in the second group of fuses based on the ECC data encoded in the subset of fuses of the first group of fuses.

Abstract: Fuse logic is configured to selectively enable certain group of fuses of a fuse array to support one of column (or row) redundancy in one application or error correction code (ECC) operations in another application. For example, the fuse logic may decode the group of fuses to enable a replacement column (or row) of memory cells in one mode or application, and decodes a subset of the group of fuses to retrieve ECC data corresponding to a second group of fuses are encoded to enable a different replacement column or row of memory cells in a second mode or application. The fuse logic includes an ECC decode logic circuit that is selectively enabled to detect and correct errors in data encoded in the second group of fuses based on the ECC data encoded in the subset of fuses of the first group of fuses.

Abstract: A method of forming a microelectronic device comprises forming a first microelectronic device structure comprising a first semiconductor structure, a first isolation material over the first semiconductor structure, and first conductive routing structures over the first semiconductor structure and surrounded by the first isolation material. A second microelectronic device structure comprising a second semiconductor structure and a second isolation material over the second semiconductor structure is formed. The second isolation material is bonded to the first isolation material to attach the second microelectronic device structure to the first microelectronic device structure. Memory cells comprising portions of the second semiconductor structure are formed after attaching the second microelectronic device structure to the first microelectronic device structure. Control logic devices including transistors comprising portions of the first semiconductor structure are formed after forming the memory cells.

Abstract: A method of forming a microelectronic device comprises forming a first microelectronic device structure comprising a first semiconductor structure, control logic circuitry including transistors at least partially overlying the first semiconductor structure, and a first isolation material covering the first semiconductor structure and the control logic circuitry. A second microelectronic device structure comprising a second semiconductor structure and a second isolation material over the second semiconductor structure is formed. The second isolation material of the second microelectronic device structure is bonded to the first isolation material of the first microelectronic device structure to attach the second microelectronic device structure to the first microelectronic device structure. Memory cells comprising portions of the second semiconductor structure are formed after attaching the second microelectronic device structure to the first microelectronic device structure.

Abstract: Some embodiments include an integrated assembly having a memory array over a base. First sense-amplifier-circuitry is associated with the base and includes sense amplifiers directly under the memory array. Vertically-extending digit lines are associated with the memory array and are coupled with the first sense-amplifier-circuitry. Second sense-amplifier-circuitry is associated with the base and is offset from the first sense-amplifier-circuitry. Control circuitry is configured to selectively couple the digit lines to either a voltage supply terminal or to the second sense-amplifier-circuitry.

Abstract: Some embodiments include an integrated assembly having a memory array over a base. First sense-amplifier-circuitry is associated with the base and includes sense amplifiers directly under the memory array. Vertically-extending digit lines are associated with the memory array and are coupled with the first sense-amplifier-circuitry. Second sense-amplifier-circuitry is associated with the base and is offset from the first sense-amplifier-circuitry. Control circuitry is configured to selectively couple the digit lines to either a voltage supply terminal or to the second sense-amplifier-circuitry.

Abstract: A multi-mode voltage pump may be configured to select an operational mode based on a temperature of a semiconductor device. The selected mode for a range of temperature values may be determined based on process variations and operational differences caused by temperature changes. The different selected modes of operation of the multi-mode voltage pump may provide pumped voltage having different voltage magnitudes. For example, the multi-mode voltage pump may operate in a first mode that uses two stages to provide a first VPP voltage, a second mode that uses a single stage to provide a second VPP voltage, or a third mode that uses a mixture of a single stage and two stages to provide a third VPP voltage. The third VPP voltage may be between the first and second VPP voltages, with the first VPP voltage having the greatest magnitude. Control signal timing of circuitry of the multi-mode voltage pump may be based on an oscillator signal.

Abstract: An access line multiplexor can be formed under vertically stacked tiers of memory cells. The multiplexor can include a first transistor coupled to a vertical access line, to a horizontal access line, and to a second transistor. The second transistor can be coupled to a power supply. The transistors can be n-type metal oxide semiconductor transistors.

Abstract: An access line multiplexor can be formed under vertically stacked tiers of memory cells. The multiplexor can include a first transistor coupled to a vertical access line, to a horizontal access line, and to a second transistor. The second transistor can be coupled to a power supply. The transistors can be n-type metal oxide semiconductor transistors.

Abstract: Some embodiments include an integrated assembly having a memory array over a base. First sense-amplifier-circuitry is associated with the base and includes sense amplifiers directly under the memory array. Vertically-extending digit lines are associated with the memory array and are coupled with the first sense-amplifier-circuitry. Second sense-amplifier-circuitry is associated with the base and is offset from the first sense-amplifier-circuitry. Control circuitry is configured to selectively couple the digit lines to either a voltage supply terminal or to the second sense-amplifier-circuitry.

Abstract: A multi-mode voltage pump may be configured to select an operational mode based on a temperature of a semiconductor device. The selected mode for a range of temperature values may be determined based on process variations and operational differences caused by temperature changes. The different selected modes of operation of the multi-mode voltage pump may provide pumped voltage having different voltage magnitudes. For example, the multi-mode voltage pump may operate in a first mode that uses two stages to provide a first VPP voltage, a second mode that uses a single stage to provide a second VPP voltage, or a third mode that uses a mixture of a single stage and two stages to provide a third VPP voltage. The third VPP voltage may be between the first and second VPP voltages, with the first VPP voltage having the greatest magnitude. Control signal timing of circuitry of the multi-mode voltage pump may be based on an oscillator signal.

Abstract: Fuse logic is configured to selectively enable certain group of fuses of a fuse array to support one of column (or row) redundancy in one application or error correction code (ECC) operations in another application. For example, the fuse logic may decode the group of fuses to enable a replacement column (or row) of memory cells in one mode or application, and decodes a subset of the group of fuses to retrieve ECC data corresponding to a second group of fuses are encoded to enable a different replacement column or row of memory cells in a second mode or application. The fuse logic includes an ECC decode logic circuit that is selectively enabled to detect and correct errors in data encoded in the second group of fuses based on the ECC data encoded in the subset of fuses of the first group of fuses.

Abstract: A multi-mode voltage pump may be configured to select an operational mode based on a temperature of a semiconductor device. The selected mode for a range of temperature values may be determined based on process variations and operational differences caused by temperature changes. The different selected modes of operation of the multi-mode voltage pump may provide pumped voltage having different voltage magnitudes. For example, the multi-mode voltage pump may operate in a first mode that uses two stages to provide a first VPP voltage, a second mode that uses a single stage to provide a second VPP voltage, or a third mode that uses a mixture of a single stage and two stages to provide a third VPP voltage. The third VPP voltage may be between the first and second VPP voltages, with the first VPP voltage having the greatest magnitude. Control signal timing of circuitry of the multi-mode voltage pump may be based on an oscillator signal.

Abstract: An apparatus may include a refresh control circuit with multiple timing circuits. The timing circuits may be used to control steal rates, e.g., the rate of refresh time slots dedicated to healing victim word lines of row hammers. The timing circuits may be controlled to allow independent adjustment of the steal rates for different victim word lines. Thus, different victim word lines may be refreshed at different rates and the different rates may be independent of one another.