Patents by Inventor Beau D. Barry

Beau D. Barry has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220311335
    Abstract: A multi-mode voltage pump may be configured to select an operational mode based on a temperature of a semiconductor device. The selected mode for a range of temperature values may be determined based on process variations and operational differences caused by temperature changes. The different selected modes of operation of the multi-mode voltage pump may provide pumped voltage having different voltage magnitudes. For example, the multi-mode voltage pump may operate in a first mode that uses two stages to provide a first VPP voltage, a second mode that uses a single stage to provide a second VPP voltage, or a third mode that uses a mixture of a single stage and two stages to provide a third VPP voltage. The third VPP voltage may be between the first and second VPP voltages, with the first VPP voltage having the greatest magnitude. Control signal timing of circuitry of the multi-mode voltage pump may be based on an oscillator signal.
    Type: Application
    Filed: June 14, 2022
    Publication date: September 29, 2022
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Dong Pan, Beau D. Barry, Liang Liu
  • Patent number: 11443780
    Abstract: An access line multiplexor can be formed under vertically stacked tiers of memory cells. The multiplexor can include a first transistor coupled to a vertical access line, to a horizontal access line, and to a second transistor. The second transistor can be coupled to a power supply. The transistors can be n-type metal oxide semiconductor transistors.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: September 13, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Yuan He, Beau D. Barry, Tae H. Kim, Christopher J. Kawamura
  • Publication number: 20220254388
    Abstract: An access line multiplexor can be formed under vertically stacked tiers of memory cells. The multiplexor can include a first transistor coupled to a vertical access line, to a horizontal access line, and to a second transistor. The second transistor can be coupled to a power supply. The transistors can be n-type metal oxide semiconductor transistors.
    Type: Application
    Filed: February 10, 2021
    Publication date: August 11, 2022
    Inventors: Yuan He, Beau D. Barry, Tae H. Kim, Christopher J. Kawamura
  • Publication number: 20220223196
    Abstract: Some embodiments include an integrated assembly having a memory array over a base. First sense-amplifier-circuitry is associated with the base and includes sense amplifiers directly under the memory array. Vertically-extending digit lines are associated with the memory array and are coupled with the first sense-amplifier-circuitry. Second sense-amplifier-circuitry is associated with the base and is offset from the first sense-amplifier-circuitry. Control circuitry is configured to selectively couple the digit lines to either a voltage supply terminal or to the second sense-amplifier-circuitry.
    Type: Application
    Filed: January 11, 2021
    Publication date: July 14, 2022
    Applicant: Micron Technology, Inc.
    Inventors: Yuan He, Beau D. Barry
  • Patent number: 11374488
    Abstract: A multi-mode voltage pump may be configured to select an operational mode based on a temperature of a semiconductor device. The selected mode for a range of temperature values may be determined based on process variations and operational differences caused by temperature changes. The different selected modes of operation of the multi-mode voltage pump may provide pumped voltage having different voltage magnitudes. For example, the multi-mode voltage pump may operate in a first mode that uses two stages to provide a first VPP voltage, a second mode that uses a single stage to provide a second VPP voltage, or a third mode that uses a mixture of a single stage and two stages to provide a third VPP voltage. The third VPP voltage may be between the first and second VPP voltages, with the first VPP voltage having the greatest magnitude. Control signal timing of circuitry of the multi-mode voltage pump may be based on an oscillator signal.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: June 28, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Dong Pan, Beau D. Barry, Liang Liu
  • Publication number: 20220019500
    Abstract: Fuse logic is configured to selectively enable certain group of fuses of a fuse array to support one of column (or row) redundancy in one application or error correction code (ECC) operations in another application. For example, the fuse logic may decode the group of fuses to enable a replacement column (or row) of memory cells in one mode or application, and decodes a subset of the group of fuses to retrieve ECC data corresponding to a second group of fuses are encoded to enable a different replacement column or row of memory cells in a second mode or application. The fuse logic includes an ECC decode logic circuit that is selectively enabled to detect and correct errors in data encoded in the second group of fuses based on the ECC data encoded in the subset of fuses of the first group of fuses.
    Type: Application
    Filed: July 15, 2020
    Publication date: January 20, 2022
    Applicant: Micron Technology, Inc.
    Inventor: Beau D. Barry
  • Publication number: 20210359598
    Abstract: A multi-mode voltage pump may be configured to select an operational mode based on a temperature of a semiconductor device. The selected mode for a range of temperature values may be determined based on process variations and operational differences caused by temperature changes. The different selected modes of operation of the multi-mode voltage pump may provide pumped voltage having different voltage magnitudes. For example, the multi-mode voltage pump may operate in a first mode that uses two stages to provide a first VPP voltage, a second mode that uses a single stage to provide a second VPP voltage, or a third mode that uses a mixture of a single stage and two stages to provide a third VPP voltage. The third VPP voltage may be between the first and second VPP voltages, with the first VPP voltage having the greatest magnitude. Control signal timing of circuitry of the multi-mode voltage pump may be based on an oscillator signal.
    Type: Application
    Filed: December 4, 2018
    Publication date: November 18, 2021
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Dong Pan, Beau D. Barry, Liang Liu
  • Publication number: 20210304813
    Abstract: An apparatus may include a refresh control circuit with multiple timing circuits. The timing circuits may be used to control steal rates, e.g., the rate of refresh time slots dedicated to healing victim word lines of row hammers. The timing circuits may be controlled to allow independent adjustment of the steal rates for different victim word lines. Thus, different victim word lines may be refreshed at different rates and the different rates may be independent of one another.
    Type: Application
    Filed: June 15, 2021
    Publication date: September 30, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Timothy B. Cowles, Jiyun Li, Beau D. Barry, Matthew D. Jenkinson, Nathaniel J. Meier, Michael A. Shore, Adam J. Grenzebach, Dennis G. Montierth
  • Publication number: 20210272620
    Abstract: Apparatuses, systems, and methods for address based memory performance. A memory array may include a first performance region and a second performance region, each of which may have different performance characteristics from each other. The second region may be distinguished from the first region based on the addresses which are associated with each region. The second performance region may have different performance characteristics based on differences in the layout, components, logic circuits, and combinations thereof. For example, the second region, compared to the first region, may have reduced difference to the data terminals, reduced length of digit lines, a different type of sense amplifier, different refresh address tracking, and combinations thereof. The controller may perform access operations on the memory with different timing based on which region of the memory is accessed.
    Type: Application
    Filed: February 26, 2021
    Publication date: September 2, 2021
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Beau D. Barry
  • Patent number: 11069393
    Abstract: An apparatus may include a refresh control circuit with multiple timing circuits. The timing circuits may be used to control steal rates, e.g., the rate of refresh time slots dedicated to healing victim word lines of row hammers. The timing circuits may be controlled to allow independent adjustment of the steal rates for different victim word lines. Thus, different victim word lines may be refreshed at different rates and the different rates may be independent of one another.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: July 20, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Timothy B. Cowles, Jiyun Li, Beau D. Barry, Matthew D. Jenkinson, Nathaniel J. Meier, Michael A. Shore, Adam J. Grenzebach, Dennis G. Montierth
  • Publication number: 20200388325
    Abstract: An apparatus may include a refresh control circuit with multiple timing circuits. The timing circuits may be used to control steal rates, e.g., the rate of refresh time slots dedicated to healing victim word lines of row hammers. The timing circuits may be controlled to allow independent adjustment of the steal rates for different victim word lines. Thus, different victim word lines may be refreshed at different rates and the different rates may be independent of one another.
    Type: Application
    Filed: June 4, 2019
    Publication date: December 10, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Timothy B. Cowles, Jiyun Li, Beau D. Barry, Matthew D. Jenkinson, Nathaniel J. Meier, Michael A. Shore, Adam J. Grenzebach, Dennis G. Montierth
  • Patent number: 10854274
    Abstract: Apparatuses, systems and methods for dynamic timing of row pull-down operations are described herein. When a word line is accessed, the row decoder may drive that word line to an active voltage, and then to an intermediate voltage. The row decoder may maintain that word line at the intermediate voltage until another word line in the same group of word lines as the accessed word line receives an access command, at which point the first word line is driven to an inactive voltage. For example, if the word lines are grouped by bank, then after an access to a first word line, the first word line may be maintained at the intermediate voltage until a second wordline in the same bank as the first word line is accessed. This may help to mitigate the effect on other nearby word lines of driving a word line to the inactive voltage.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: December 1, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Adam J. Grenzebach, Timothy B. Cowles, Beau D. Barry
  • Patent number: 9202550
    Abstract: Examples described include precharge operations and circuitry for performing precharge operations. Digit lines may be driven to ground during a portion of example precharge operations. By driving the digit lines to ground, charge accumulating in bodies of vertical access devices may be discharged to the digit lines in some examples. To drive the digit lines to ground, a dynamic reference may be used where the reference is ground during one portion of the precharge operation and another value, which may be between two supply voltages (e.g. VCC/2), during another portion of the precharge operation.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: December 1, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Beau D. Barry
  • Publication number: 20140029365
    Abstract: Examples described include precharge operations and circuitry for performing precharge operations. Digit lines may be driven to ground during a portion of example precharge operations. By driving the digit lines to ground, charge accumulating in bodies of vertical access devices may be discharged to the digit lines in some examples. To drive the digit lines to ground, a dynamic reference may be used where the reference is ground during one portion of the precharge operation and another value, which may be between two supply voltages (e.g. VCC/2), during another portion of the precharge operation.
    Type: Application
    Filed: July 27, 2012
    Publication date: January 30, 2014
    Applicant: Micron Technology, Inc
    Inventor: Beau D. Barry