Patents by Inventor Belgacem Haba

Belgacem Haba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11387202
    Abstract: A nanowire bonding interconnect for fine-pitch microelectronics is provided. Vertical nanowires created on conductive pads provide a debris-tolerant bonding layer for making direct metal bonds between opposing pads or vias. Nanowires may be grown from a nanoporous medium with a height between 200-1000 nanometers and a height-to-diameter aspect ratio that enables the nanowires to partially collapse against the opposing conductive pads, creating contact pressure for nanowires to direct-bond to opposing pads. Nanowires may have diameters less than 200 nanometers and spacing less than 1 ?m from each other to enable contact or direct-bonding between pads and vias with diameters under 5 ?m at very fine pitch. The nanowire bonding interconnects may be used with or without tinning, solders, or adhesives.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: July 12, 2022
    Assignee: Invensas LLC
    Inventors: Belgacem Haba, Ilyas Mohammed
  • Patent number: 11385278
    Abstract: A bonded structure is disclosed. The bonded structure can include a first semiconductor element having a first front side and a first back side opposite the first front side. The bonded structure can include a second semiconductor element having a second front side and a second back side opposite the second front side, the first front side of the first semiconductor element directly bonded to the second front side of the second semiconductor element along a bond interface without an adhesive. The bonded structure can include security circuitry extending across the bond interface, the security circuitry electrically connected to the first and second semiconductor elements.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: July 12, 2022
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Javier A. DeLaCruz, Belgacem Haba, Guy Regev
  • Publication number: 20220216180
    Abstract: Techniques and arrangements for performing exposure operations on a wafer utilizing both a stepper apparatus and an aligner apparatus. The exposure operations are performed with respect to large composite base dies, e.g., interposers, defined within the wafer, where the interposers will become a part of microelectronic devices by coupling with active dies or microchips. The composite base dies may be coupled to the active dies via “native interconnects” utilizing direct bonding techniques. The stepper apparatus may be used to perform exposure operations on active regions of the composite base dies to provide a fine pitch for the native interconnects, while the aligner apparatus may be used to perform exposure operations on inactive regions of the composite base dies to provide a coarse pitch for interfaces with passive regions of the composite base dies.
    Type: Application
    Filed: January 19, 2022
    Publication date: July 7, 2022
    Inventors: Javier A. Delacruz, Belgacem Haba
  • Publication number: 20220208723
    Abstract: Embodiments of methods for producing direct bonded structures and methods for forming direct bonded structures are disclosed. The direct bonded structures may include elements comprising active electronics, microelectromechanical systems, optical elements, and so forth.
    Type: Application
    Filed: December 29, 2021
    Publication date: June 30, 2022
    Inventors: Rajesh Katkar, Belgacem Haba, Paul M. Enquist, Gaius Gillman Fountain, JR., Guilian Gao, Cyprian Emeka Uzoh
  • Patent number: 11373963
    Abstract: A bonded structure is disclosed. The bonded structure can include a semiconductor element comprising active circuitry. The bonded structure can include a protective element directly bonded to the semiconductor element without an adhesive along a bonding interface. The protective element can include an obstructive material disposed over at least a portion of the active circuitry. The obstructive material can be configured to obstruct external access to the active circuitry. The bonded structure can include a disruption structure configured to disrupt functionality of the at least a portion of the active circuitry upon debonding of the protective element from the semiconductor element.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: June 28, 2022
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Javier A. DeLaCruz, Belgacem Haba, Rajesh Katkar
  • Publication number: 20220199560
    Abstract: A bonded structure can include a first reconstituted element comprising a first element and having a first side comprising a first bonding surface and a second side opposite the first side. The first reconstituted element can comprise a first protective material disposed about a first sidewall surface of the first element. The bonded structure can comprise a second reconstituted element comprising a second element and having a first side comprising a second bonding surface and a second side opposite the first side. The first reconstituted element can comprise a second protective material disposed about a second sidewall surface of the second element. The second bonding surface of the first side of the second reconstituted element can be directly bonded to the first bonding surface of the first side of the first reconstituted element without an intervening adhesive along a bonding interface.
    Type: Application
    Filed: December 28, 2021
    Publication date: June 23, 2022
    Inventors: Belgacem Haba, Rajesh Katkar, Ilyas Mohammed, Javier A. DeLaCruz
  • Patent number: 11369020
    Abstract: A stacked, multi-layer transmission line is provided. The stacked transmission line includes at least a pair of conductive traces, each conductive trace having a plurality of conductive stubs electrically coupled thereto. The stubs are disposed in one or more separate spatial layers from the conductive traces.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: June 21, 2022
    Assignee: Invensas LLC
    Inventors: Shaowu Huang, Javier A. Delacruz, Belgacem Haba
  • Publication number: 20220189941
    Abstract: Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.
    Type: Application
    Filed: January 27, 2022
    Publication date: June 16, 2022
    Inventors: Paul M. Enquist, Belgacem Haba
  • Patent number: 11348898
    Abstract: An integrated circuit and a method for designing an IC wherein the base or host chip is bonded to smaller chiplets via DBI technology. The bonding of chip to chiplet creates an uneven or multi-level surface of the overall chip requiring a releveling for future bonding. The uneven surface is built up with plating of bumps and subsequently releveled with various methods including planarization.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: May 31, 2022
    Assignee: Xcelsis Corporation
    Inventors: Javier A. Delacruz, Belgacem Haba, Cyprian Emeka Uzoh, Rajesh Katkar, Ilyas Mohammed
  • Publication number: 20220155490
    Abstract: Direct-bonded lamination for improved image clarity in optical devices is provided. An example process planarizes and plasma-activates optical surfaces to be laminated together, then forms direct bonds between the two surfaces without an adhesive or adhesive layer. This process provides improved optics with higher image brightness, less light scattering, better resolution, and higher image fidelity. The direct bonds also provide a refractory interface tolerant of much higher temperatures than conventional optical adhesives. The example process can be used to produce many types of improved optical components, such as improved laminated lenses, mirrors, beam splitters, collimators, prism systems, optical conduits, and mirrored waveguides for smartglasses and head-up displays (HUDs), which provide better image quality and elimination of the dark visual lines that are apparent to a human viewer when conventional adhesives are used in conventional lamination.
    Type: Application
    Filed: January 28, 2022
    Publication date: May 19, 2022
    Inventors: Belgacem Haba, Rajesh Katkar, Ilyas MOHAMMED
  • Publication number: 20220150184
    Abstract: The technology relates to a system on chip (SoC). The SoC may include a plurality of network layers which may assist electrical communications either horizontally or vertically among components from different device layers. In one embodiment, a system on chip (SoC) includes a plurality of network layers, each network layer including one or more routers, and more than one device layers, each of the plurality of network layers respectively bonded to one of the device layers. In another embodiment, a method for forming a system on chip (SoC) includes forming a plurality of network layers in an interconnect, wherein each network layer is bonded to an active surface of a respective device layer in a plurality of device layer.
    Type: Application
    Filed: January 25, 2022
    Publication date: May 12, 2022
    Applicant: Invensas Corporation
    Inventors: Javier A. DeLaCruz, Belgacem Haba, Rajesh Katkar
  • Publication number: 20220139883
    Abstract: The technology relates to a system on chip (SoC). The SoC may include a network on layer including one or more routers and an application specific integrated circuit (ASIC) layer bonded to the network layer, the ASIC layer including one or more components. In some instances, the network layer and the ASIC layer each include an active surface and a second surface opposite the active surface. The active surface of the ASIC layer and the second surface of the network may each include one or more contacts, and the network layer may be bonded to the ASIC layer via bonds formed between the one or more contacts on the second surface of the network layer and the one or more contacts on the active surface of the ASIC layer.
    Type: Application
    Filed: January 18, 2022
    Publication date: May 5, 2022
    Applicant: Invensas Corporation
    Inventors: Javier A. DeLaCruz, Belgacem Haba
  • Publication number: 20220122934
    Abstract: In one embodiment, an integrated device package is disclosed. The integrated device package can comprise a carrier an a molding compound over a portion of an upper surface of the carrier. The integrated device package can comprise an integrated device die mounted to the carrier and at least partially embedded in the molding compound, the integrated device die comprising active circuitry. The integrated device package can comprise a stress compensation element mounted to the carrier and at least partially embedded in the molding compound, the stress compensation element spaced apart from the integrated device die, the stress compensation element comprising a dummy stress compensation element devoid of active circuitry. At least one of the stress compensation element and the integrated device die can be directly bonded to the carrier without an adhesive.
    Type: Application
    Filed: December 28, 2021
    Publication date: April 21, 2022
    Inventor: Belgacem Haba
  • Patent number: 11296053
    Abstract: Direct bonded stack structures for increased reliability and improved yields in microelectronics are provided. Structural features and stack configurations are provided for memory modules and 3DICs to reduce defects in vertically stacked dies. Example processes alleviate warpage stresses between a thicker top die and direct bonded dies beneath it, for example. An etched surface on the top die may relieve warpage stresses. An example stack may include a compliant layer between dies. Another stack configuration replaces the top die with a layer of molding material to circumvent warpage stresses. An array of cavities on a bonding surface can alleviate stress forces. One or more stress balancing layers may also be created on a side of the top die or between other dies to alleviate or counter warpage. Rounding of edges can prevent stresses and pressure forces from being destructively transmitted through die and substrate layers. These measures may be applied together or in combinations in a single package.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: April 5, 2022
    Assignee: INVENSAS BONDING TECHNOLOGIES, INC.
    Inventors: Cyprian Emeka Uzoh, Rajesh Katkar, Thomas Workman, Guilian Gao, Gaius Gillman Fountain, Jr., Laura Wills Mirkarimi, Belgacem Haba, Gabriel Z. Guevara, Joy Watanabe
  • Patent number: 11276676
    Abstract: Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: March 15, 2022
    Assignee: INVENSAS BONDING TECHNOLOGIES, INC.
    Inventors: Paul M. Enquist, Belgacem Haba
  • Publication number: 20220077063
    Abstract: A bonded structure is disclosed. The bonded structure can include an interconnect structure that has a first side and a second side opposite the first side. The bonded structure can also include a first die that is mounted to the first side of the interconnect structure. The first die can be directly bonded to the interconnect structure without an intervening adhesive. The bonded structure can also include a second die that is mounted to the first side of the interconnect structure. The bonded structure can further include an element that is mounted to the second side of the interconnect structure. The first die and the second die are electrically connected by way of at least the interconnect structure and the element.
    Type: Application
    Filed: February 9, 2021
    Publication date: March 10, 2022
    Inventor: Belgacem Haba
  • Publication number: 20220077087
    Abstract: A bonded structure is disclosed. The bonded structure can include an interconnect structure. The bonded structure can also include a first die directly bonded to the interconnect structure. The bonded structure can also include a second die mounted to the interconnect structure. The second die is spaced apart from the first die laterally along an upper surface of the interconnect structure. The second die is electrically connected with the first die at least partially through the interconnect structure. The bonded structure can further include a dielectric layer that is disposed over the upper surface of the interconnect structure between the first die and the second die.
    Type: Application
    Filed: February 9, 2021
    Publication date: March 10, 2022
    Inventor: Belgacem Haba
  • Patent number: 11270979
    Abstract: The technology relates to a system on chip (SoC). The SoC may include a plurality of network layers which may assist electrical communications either horizontally or vertically among components from different device layers. In one embodiment, a system on chip (SoC) includes a plurality of network layers, each network layer including one or more routers, and more than one device layers, each of the plurality of network layers respectively bonded to one of the device layers. In another embodiment, a method for forming a system on chip (SoC) includes forming a plurality of network layers in an interconnect, wherein each network layer is bonded to an active surface of a respective device layer in a plurality of device layer.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: March 8, 2022
    Assignee: Invensas Corporation
    Inventors: Javier A. Delacruz, Belgacem Haba, Rajesh Katkar
  • Patent number: 11264361
    Abstract: The technology relates to a system on chip (SoC). The SoC may include a network on layer including one or more routers and an application specific integrated circuit (ASIC) layer bonded to the network layer, the ASIC layer including one or more components. In some instances, the network layer and the ASIC layer each include an active surface and a second surface opposite the active surface. The active surface of the ASIC layer and the second surface of the network may each include one or more contacts, and the network layer may be bonded to the ASIC layer via bonds formed between the one or more contacts on the second surface of the network layer and the one or more contacts on the active surface of the ASIC layer.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: March 1, 2022
    Assignee: Invensas Corporation
    Inventors: Javier A. Delacruz, Belgacem Haba
  • Patent number: 11264357
    Abstract: Techniques and arrangements for performing exposure operations on a wafer utilizing both a stepper apparatus and an aligner apparatus. The exposure operations are performed with respect to large composite base dies, e.g., interposers, defined within the wafer, where the interposers will become a part of microelectronic devices by coupling with active dies or microchips. The composite base dies may be coupled to the active dies via “native interconnects” utilizing direct bonding techniques. The stepper apparatus may be used to perform exposure operations on active regions of the composite base dies to provide a fine pitch for the native interconnects, while the aligner apparatus may be used to perform exposure operations on inactive regions of the composite base dies to provide a coarse pitch for interfaces with passive regions of the composite base dies.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: March 1, 2022
    Assignee: Invensas Corporation
    Inventors: Javier A. Delacruz, Belgacem Haba