Patents by Inventor Bendik Kleveland

Bendik Kleveland has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090015342
    Abstract: A startup circuit 200 and method 700 is provided for quickly starting up a resonator based oscillator. Tunable oscillator 201 provides an impetus signal to oscillator 205 through capacitor 202. The impetus signal has a frequency that is an estimate of the resonant frequency of resonator 205. The circuit measures the frequency of oscillator 204 and the frequency of tunable oscillator 201. The circuit then adjusts the frequency of tunable oscillator 201 such that the frequency of the tunable oscillator is substantially equal to the resonant frequency of the resonator 205 and stores a data state necessary for the tunable oscillator 201 to generate a signal with this target frequency in the future. During an ensuing startup cycle the stored data state causes the impetus signal delivered by tunable oscillator 202 to be substantially equal to the target frequency of oscillator 204 which improves startup performance.
    Type: Application
    Filed: July 12, 2007
    Publication date: January 15, 2009
    Applicant: ZeroG Wireless, Inc.
    Inventor: Bendik Kleveland
  • Publication number: 20080278247
    Abstract: A calibration circuit (20, 50) and method (60) for calibrating the bias current of a VCO (10, 40) to minimize phase noise. The calibration circuit (20, 50) monitors the average voltage at the common-mode node of the VCO (10, 40) while varying the bias current over a predetermined range. The calibration circuit (20, 50) identifies the bias current associated with the minimum average common-mode voltage and utilizes this bias current for calibrating the biasing transistor of the VCO (10, 40).
    Type: Application
    Filed: July 10, 2008
    Publication date: November 13, 2008
    Applicant: ZEROG WIRELESS, INC.
    Inventors: Stanley Wang, Bendik Kleveland, Thomas H. Lee
  • Publication number: 20080278252
    Abstract: A calibration circuit (20, 50) and method (60) for calibrating the bias current of a VCO (10, 40) to minimize phase noise. The calibration circuit (20, 50) monitors the average voltage at the common-mode node of the VCO (10, 40) while varying the bias current over a predetermined range. The calibration circuit (20, 50) identifies the bias current associated with the minimum average common-mode voltage and utilizes this bias current for calibrating the biasing transistor of the VCO (10, 40).
    Type: Application
    Filed: July 10, 2008
    Publication date: November 13, 2008
    Applicant: ZEROG WIRELESS, INC.
    Inventors: Stanley Wang, Bendik Kleveland, Thomas H. Lee
  • Patent number: 7415369
    Abstract: A calibration circuit (20, 50) and method (60) for calibrating the bias current of a VCO (10, 40) to minimize phase noise. The calibration circuit (20, 50) monitors the average voltage at the common-mode node of the VCO (10, 40) while varying the bias current over a predetermined range. The calibration circuit (20, 50) identifies the bias current associated with the minimum average common-mode voltage and utilizes this bias current for calibrating the biasing transistor of the VCO (10, 40).
    Type: Grant
    Filed: May 8, 2007
    Date of Patent: August 19, 2008
    Inventors: Stanley Wang, Bendik Kleveland, Thomas H. Lee
  • Publication number: 20080169866
    Abstract: A combined charge storage and bandgap reference is disclosed. In one embodiment, a system comprises a bandgap reference circuit; a charge storage circuit, wherein an output of the bandgap reference circuit is provided as an input to the charge storage circuit; and a control circuit in communication with the bandgap reference circuit and the charge storage circuit. The control circuit is operative to control charging of the charge storage circuit by the output of the bandgap reference circuit and control selection of one of the output of the bandgap reference circuit and an output of the charge storage circuit. Other embodiments are disclosed, and each of the embodiments can be used alone or together in combination.
    Type: Application
    Filed: January 16, 2007
    Publication date: July 17, 2008
    Inventors: Bendik Kleveland, Thomas H. Lee
  • Patent number: 7383476
    Abstract: In one embodiment, a chip-level architecture is provided comprising a monolithic three-dimensional write-once memory array and at least two of the following system blocks: an Error Checking & Correction Circuit (ECC); a Checkerboard Memory Array containing sub arrays; a Write Controller; a Charge Pump; a Vread Generator; an Oscillator; a Band Gap Reference Generator; and a Page Register/Fault Memory. In another embodiment, a chip-level architecture is provided comprising a monolithic three-dimensional write-once memory array, ECC, and smart write. The monolithic three-dimensional write-once memory array comprises a first conductor, a first memory cell above the first conductor, a second conductor above the first memory cell, and a second memory cell above the second conductor, wherein the second conductor is the only conductor between the first and second memory cells.
    Type: Grant
    Filed: February 9, 2004
    Date of Patent: June 3, 2008
    Assignee: SanDisk 3D LLC
    Inventors: Matthew P. Crowley, Luca G. Fasoli, Alper Ilkbahar, Mark G. Johnson, Bendik Kleveland, Thomas H. Lee, Roy E. Scheuerlein
  • Publication number: 20080084919
    Abstract: In a wireless transmission method, an input data signal corresponding to a serial combination of a first transmit data signal and a second transmit data signal is received. The first and second transmit data signals are phase-modulated with different first and second spreading code signals to produce first and second DSSS transmit signals, which are serially output as a baseband transmit signal that is up-converted to a selected wireless transmission frequency range. The first and second phase-modulated signals are serially output as a baseband transmit signal. In a wireless reception method, an input receive signal is down-converted to a baseband receive signal corresponding to a serial combination of first and second time-interleaved DSSS receive signals in a baseband frequency range. The first and second DSSS receive signals are phase-demodulated with different first and second de-spreading code signals to produce first and second receive data signals.
    Type: Application
    Filed: November 30, 2006
    Publication date: April 10, 2008
    Inventors: Bendik Kleveland, David Friedman, Stanley B-T Wang, Thomas H. Lee, Carl Gyllenhammer
  • Publication number: 20080084922
    Abstract: Multiprotocol multiplex wireless communication apparatus and methods are described. These apparatus and methods are capable of simultaneously communicating with multiple wireless environments in accordance with different wireless communications protocols. In particular, these apparatus and methods are capable of transmitting and receiving multiplex signals that include constituent data-carrying signals that conform to different wireless communications protocols.
    Type: Application
    Filed: October 5, 2006
    Publication date: April 10, 2008
    Inventors: Bendik Kleveland, David Friedman, Stanley B-T Wang, Thomas Lee, Carl Gyllenhammer
  • Publication number: 20070115160
    Abstract: Apparatus and methods of differentially decoding analog baseband signals are described. In one aspect, a wireless communication apparatus includes a baseband filtering stage and a differential decoder stage. The baseband filtering stage receives a DPSK analog baseband signal differentially encoded with phase shift differences in successive symbol periods. The baseband filtering stage selectively passes frequencies in the DPSK analog baseband signal within a passband frequency range to produce a filtered analog signal. The differential decoder includes a delay circuit and a combiner circuit. The delay circuit produces from the filtered analog signal a reference signal that preserves values of a feature of the filtered analog signal for one symbol period. The combiner circuit combines values of a feature of the filtered analog signal during a current symbol period with values of the reference signal to produce a resultant signal representing a differential decoding of the DPSK analog baseband signal.
    Type: Application
    Filed: November 16, 2006
    Publication date: May 24, 2007
    Inventors: Bendik Kleveland, Junfeng Xu, Thomas Lee, Dickson Wong
  • Patent number: 7219271
    Abstract: The preferred embodiments described herein provide a memory device and method for redundancy/self-repair. In one preferred embodiment, a memory device is provided comprising a primary block of memory cells and a redundant block of memory cells. In response to an error in writing to the primary block, a flag is stored in a set of memory cells allocated to the primary block, and the redundant block is written into. In another preferred embodiment, an error in writing to a primary block is detected while an attempt is made to write to that block. In response to the error, the redundant block is written into. In yet another preferred embodiment, a memory device is provided comprising a three-dimensional memory array and redundancy circuitry. In still another preferred embodiment, a method for testing a memory array is provided. Other preferred embodiments are provided, and each of the preferred embodiments described herein can be used alone or in combination with one another.
    Type: Grant
    Filed: December 14, 2001
    Date of Patent: May 15, 2007
    Assignee: SanDisk 3D LLC
    Inventors: Bendik Kleveland, Alper Ilkbahar, Roy E. Scheuerlein
  • Patent number: 7212454
    Abstract: A method and apparatus for programming a memory array are disclosed. In one embodiment, after each word line is programmed, an attempt is made to detect a defect on that word line. If a defect is detected, the word line is repaired with a redundant word line. The word lines are then reprogrammed and rechecked for defects. In another embodiment, after each word line is programmed, an attempt is made to detect a defect on that word line. If a defect is detected, that word line is repaired along with a previously-programmed adjacent word line. In yet another embodiment, after each word line is programmed, an attempt is made to detect a defect on that word line and a previously-programmed adjacent word line. If a defect is detected on that word line, that word line and the previously-programmed adjacent word line are repaired with redundant word lines.
    Type: Grant
    Filed: June 22, 2005
    Date of Patent: May 1, 2007
    Assignee: SanDisk 3D LLC
    Inventors: Bendik Kleveland, Tae Hee Lee, Seung Geon Yu, Chia Yang, Feng Li, Xiaoyu Yang
  • Patent number: 7180949
    Abstract: A high-speed parallel interface for communicating data between integrated circuits is disclosed. The interface is implemented by a transmitter and receiver pair and a single-ended parallel interconnect bus coupling to the transmitter and receiver pair. As opposed to transmitting small swing signals over differential signal lines, the transmitter transmits data to the receiver at full swing over the single-ended parallel interconnect bus. The invention can be implemented with simple CMOS circuitry that does not consume large die area. Accordingly, many link interfaces can be implemented on a single chip to provide a large data bandwidth.
    Type: Grant
    Filed: May 16, 2003
    Date of Patent: February 20, 2007
    Assignee: Lucent Technologies Inc.
    Inventors: Bendik Kleveland, Eric Anderson, Gunes Aybay, Philip Ferolito
  • Publication number: 20060291303
    Abstract: A method and apparatus for programming a memory array are disclosed. In one embodiment, after each word line is programmed, an attempt is made to detect a defect on that word line. If a defect is detected, the word line is repaired with a redundant word line. The word lines are then reprogrammed and rechecked for defects. In another embodiment, after each word line is programmed, an attempt is made to detect a defect on that word line. If a defect is detected, that word line is repaired along with a previously-programmed adjacent word line. In yet another embodiment, after each word line is programmed, an attempt is made to detect a defect on that word line and a previously-programmed adjacent word line. If a defect is detected on that word line, that word line and the previously-programmed adjacent word line are repaired with redundant word lines.
    Type: Application
    Filed: June 22, 2005
    Publication date: December 28, 2006
    Inventors: Bendik Kleveland, Tae Lee, Seung Yu, Chia Yang, Feng Li, Xiaoyu Yang
  • Patent number: 7134056
    Abstract: A high-speed parallel interface for communicating data between integrated circuits is disclosed. In one embodiment, the transmitter controller accepts 40-bit wide data every 167 Mhz clock cycle, the receiver controller delivers 40-bit wide data every 167 Mhz clock cycle, and the interconnect bus transmits 10-bit wide data at every transition of a 333 Mhz clock cycle. In another embodiment, the transmitter controller accepts 32-bit wide data every 167 Mhz clock cycle, the receiver controller delivers 32-bit wide data every 167 Mhz clock cycle, and the interconnect bus of this embodiment transmits 8-bit wide data at every transition of a 333 Mhz clock cycle. Output pins of the transmitter interface can be connected to any input pins of the receiver interface. Furthermore, the high-speed parallel interface does not require a fixed phase relationship between the receiver's internal clock(s) and the bus clock signal.
    Type: Grant
    Filed: May 16, 2003
    Date of Patent: November 7, 2006
    Assignee: Lucent Technologies Inc.
    Inventors: Bendik Kleveland, Eric Anderson, Gunes Aybay, Philip Ferolito
  • Patent number: 7057958
    Abstract: The preferred embodiments described herein relate to a method and system for temperature compensation for memory cells with temperature-dependent behavior. In one preferred embodiment, at least one of a first temperature-dependent reference voltage comprising a negative temperature coefficient and a second temperature-dependent reference voltage comprising a positive temperature coefficient is generated. One of a wordline voltage and a bitline voltage is generated from one of the at least one of the first and second temperature-dependent reference voltages. The other of the wordline and bitline voltages is generated, and the wordline and bitline voltages are applied across a memory cell. Other methods and systems are disclosed for sensing a memory cell comprising temperature-dependent behavior, and each of the preferred embodiments can be used alone or in combination with one another.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: June 6, 2006
    Assignee: SanDisk Corporation
    Inventors: Kenneth So, Luca Fasoli, Bendik Kleveland
  • Patent number: 6954394
    Abstract: The preferred embodiments described herein relate to an integrated circuit and method for selecting a set of memory-cell-layer-dependent or temperature-dependent operating conditions. In one preferred embodiment, a memory array is provided comprising a plurality of memory cells arranged in L layers stacked vertically above one another in a single integrated circuit. A memory cell layer in the memory array is selected, and one of N sets of memory-cell-layer-dependent writing conditions and/or one of K sets of memory-cell-layer-dependent reading conditions is selected based on the selected memory cell layer. In another preferred embodiment, a temperature of an integrated circuit is measured, and a set of writing conditions and/or a set of reading conditions is selected based on the measured temperature. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: October 11, 2005
    Assignee: Matrix Semiconductor, Inc.
    Inventors: N. Johan Knall, Roy E. Scheuerlein, James M. Cleeves, Bendik Kleveland, Mark G. Johnson
  • Patent number: 6894936
    Abstract: A memory device and method for selectable sub-array activation. In one preferred embodiment, a memory array is provided comprising a plurality of groups of sub-arrays and circuitry operative to simultaneously write data into and/or read data from a selected number of groups of sub-arrays. By selecting the number of groups of sub-arrays into which data is written and/or from which data is read, the write and/or read data rate is varied. Such varying can be used to prevent thermal run-away of the memory array. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.
    Type: Grant
    Filed: July 18, 2003
    Date of Patent: May 17, 2005
    Assignee: Matrix Semiconductor, Inc.
    Inventors: Roy E. Scheuerlein, Bendik Kleveland
  • Publication number: 20050078537
    Abstract: The preferred embodiments described herein relate to a method and system for temperature compensation for memory cells with temperature-dependent behavior. In one preferred embodiment, at least one of a first temperature-dependent reference voltage comprising a negative temperature coefficient and a second temperature-dependent reference voltage comprising a positive temperature coefficient is generated. One of a wordline voltage and a bitline voltage is generated from one of the at least one of the first and second temperature-dependent reference voltages. The other of the wordline and bitline voltages is generated, and the wordline and bitline voltages are applied across a memory cell. Other methods and systems are disclosed for sensing a memory cell comprising temperature-dependent behavior, and each of the preferred embodiments can be used alone or in combination with one another.
    Type: Application
    Filed: September 30, 2003
    Publication date: April 14, 2005
    Inventors: Kenneth So, Luca Fasoli, Bendik Kleveland
  • Publication number: 20040250183
    Abstract: This invention is directed to a chip-level architecture used in combination with a monolithic three-dimensional write-once memory array.
    Type: Application
    Filed: February 9, 2004
    Publication date: December 9, 2004
    Inventors: Matthew P. Crowley, Luca G. Fasoli, Alper Ilkbahar, Mark G. Johnson, Bendik Kleveland, Thomas H. Lee, Roy E. Scheuerlein
  • Patent number: 6816410
    Abstract: A three-dimensional memory array includes a plurality of rail-stacks on each of several levels forming alternating levels of X-lines and Y-lines for the array. Memory cells are formed at the intersection of each X-line and Y-line. The memory cells of each memory plane are all oriented in the same direction relative to the substrate, forming a serial chain diode stack. In certain embodiments, row and column circuits for the array are arranged to interchange function depending upon the directionality of memory cells in the selected memory plane. High-voltage drivers for the X-lines and Y-lines are each capable of passing a write current in either direction depending on the direction of the selected memory cell. A preferred bias arrangement reverse biases only unselected memory cells within the selected memory plane, totaling approximately N2 memory cells, rather than approximately 3N2 memory cells as with prior arrays.
    Type: Grant
    Filed: March 25, 2004
    Date of Patent: November 9, 2004
    Assignee: Matrix Semiconductor, Inc.
    Inventors: Bendik Kleveland, Roy E. Scheuerlein