Patents by Inventor Benjamin James Kerr

Benjamin James Kerr has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220300165
    Abstract: The present disclosure provides an interconnect architecture that enables communications and/or data transmissions among data storage drives in a computing system. The flash translation layer (FTL) in each data storage drive may be operated in a cooperative manner that allows communications and/or data transmissions across memory arrays from each of the data storage drives implemented in the computing system. The direct communications and/or data transmissions among the data storage drives in the computing system may be enabled without deferring back to a host computing device in the computing system. Thus, the computational load to the host computing device is reduced and the flexibility of scaling up the storage appliance in the computing system is increased.
    Type: Application
    Filed: March 22, 2021
    Publication date: September 22, 2022
    Inventors: Benjamin James Kerr, Nital Pankajkumar Patwa
  • Patent number: 11281603
    Abstract: A system for serial communication includes a controller, a semiconductor package comprising a plurality of semiconductor die, and a serial interface configured to connect the plurality of semiconductor die to the controller. The serial interface includes a controller-to-package connection and a package-to-controller connection, and the serial interface is configured to employ a signaling protocol using differential data signaling with no separate clock signals.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: March 22, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Benjamin James Kerr, Philip Rose, Robert Reed
  • Patent number: 11256634
    Abstract: A memory system for storing and retrieving data may include a controller, a first switch, a second switch connected to the first switch via an interconnecting bus, and a plurality of memory devices. The controller may have a first serial interface. The first switch may have one or more serial interfaces and one or more memory ports. The first serial interface of the controller may be communicatively connected to a first serial interface of the one or more serial interfaces of the first switch via a first serial bus. Each of the one or more memory ports of the first switch may be communicatively connected to a subset of the plurality of memory devices via a memory bus. The first switch may transfer data between the controller and the subsets of the plurality of memory devices via the one or more memory ports.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: February 22, 2022
    Assignee: Kioxia Corporation
    Inventors: Gary James Calder, Benjamin James Kerr, Philip Rose
  • Publication number: 20200293466
    Abstract: A memory system for storing and retrieving data may include a controller, a first switch, a second switch connected to the first switch via an interconnecting bus, and a plurality of memory devices. The controller may have a first serial interface. The first switch may have one or more serial interfaces and one or more memory ports. The first serial interface of the controller may be communicatively connected to a first serial interface of the one or more serial interfaces of the first switch via a first serial bus. Each of the one or more memory ports of the first switch may be communicatively connected to a subset of the plurality of memory devices via a memory bus. The first switch may transfer data between the controller and the subsets of the plurality of memory devices via the one or more memory ports.
    Type: Application
    Filed: April 27, 2020
    Publication date: September 17, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Gary James Calder, Benjamin James Kerr, Philip Rose
  • Patent number: 10720158
    Abstract: Methods of low power detection of an activation phrase are described. A microphone system comprises dedicated hardware logic for detecting a pre-defined activation phrase in an audio stream received via a microphone. If the pre-defined activation phrase is detected, the hardware logic sends a trigger signal to activate a module, such as a main speech detection module, which is external to the microphone system and which may be in a low power standby state.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: July 21, 2020
    Assignee: Imagination Technologies Limited
    Inventor: Benjamin James Kerr
  • Patent number: 10635610
    Abstract: A memory system for storing and retrieving data may include a controller, a first switch, a second switch connected to the first switch via an interconnecting bus, and a plurality of memory devices. The controller may have a first serial interface. The first switch may have one or more serial interfaces and one or more memory ports. The first serial interface of the controller may be communicatively connected to a first serial interface of the one or more serial interfaces of the first switch via a first serial bus. Each of the one or more memory ports of the first switch may be communicatively connected to a subset of the plurality of memory devices via a memory bus. The first switch may transfer data between the controller and the subsets of the plurality of memory devices via the one or more memory ports.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: April 28, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Gary James Calder, Benjamin James Kerr, Philip Rose
  • Publication number: 20200042471
    Abstract: A system for serial communication includes a controller, a semiconductor package comprising a plurality of semiconductor die, and a serial interface configured to connect the plurality of semiconductor die to the controller. The serial interface includes a controller-to-package connection and a package-to-controller connection, and the serial interface is configured to employ a signaling protocol using differential data signaling with no separate clock signals.
    Type: Application
    Filed: August 3, 2018
    Publication date: February 6, 2020
    Inventors: Benjamin James Kerr, Philip Rose, Robert Reed
  • Publication number: 20190027145
    Abstract: Methods of low power detection of an activation phrase are described. A microphone system comprises dedicated hardware logic for detecting a pre-defined activation phrase in an audio stream received via a microphone. If the pre-defined activation phrase is detected, the hardware logic sends a trigger signal to activate a module, such as a main speech detection module, which is external to the microphone system and which may be in a low power standby state.
    Type: Application
    Filed: September 25, 2018
    Publication date: January 24, 2019
    Inventor: Benjamin James KERR
  • Patent number: 10115397
    Abstract: Methods of low power detection of an activation phrase are described. A microphone system comprises dedicated hardware logic for detecting a pre-defined activation phrase in an audio stream received via a microphone. If the pre-defined activation phrase is detected, the hardware logic sends a trigger signal to activate a module, such as a main speech detection module, which is external to the microphone system and which may be in a low power standby state.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: October 30, 2018
    Assignee: Imagination Technologies Limited
    Inventor: Benjamin James Kerr
  • Publication number: 20170372698
    Abstract: Methods of low power detection of an activation phrase are described. A microphone system comprises dedicated hardware logic for detecting a pre-defined activation phrase in an audio stream received via a microphone. If the pre-defined activation phrase is detected, the hardware logic sends a trigger signal to activate a module, such as a main speech detection module, which is external to the microphone system and which may be in a low power standby state.
    Type: Application
    Filed: September 8, 2017
    Publication date: December 28, 2017
    Inventor: Benjamin James KERR
  • Patent number: 9767798
    Abstract: Methods of low power detection of an activation phrase are described. A microphone system comprises dedicated hardware logic for detecting a pre-defined activation phrase in an audio stream received via a microphone. If the pre-defined activation phrase is detected, the hardware logic sends a trigger signal to activate a module, such as a main speech detection module, which is external to the microphone system and which may be in a low power standby state.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: September 19, 2017
    Assignee: Imagination Technologies Limited
    Inventor: Benjamin James Kerr
  • Publication number: 20160253997
    Abstract: Methods of low power detection of an activation phrase are described. A microphone system comprises dedicated hardware logic for detecting a pre-defined activation phrase in an audio stream received via a microphone. If the pre-defined activation phrase is detected, the hardware logic sends a trigger signal to activate a module, such as a main speech detection module, which is external to the microphone system and which may be in a low power standby state.
    Type: Application
    Filed: March 20, 2015
    Publication date: September 1, 2016
    Inventor: Benjamin James KERR
  • Patent number: 8766693
    Abstract: The present invention provides an improvement of a 4-quadrant clock phase interpolator design to allow independent rotation of the output clocks in steps of 90°. This feature is useful in clock/data recovery where the 90° “jumps” can be used as a coarse control to re-align the data capture clock to achieve any desired data word alignment and/or receive bus clock alignment. The phase interpolator has a switching circuit comprising a single level of switches; a set of four transistor loads; and a set of four current sources operable to be switched by the switching circuit through to any of the set of four transistor loads.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: July 1, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Andrew Pickering, Andrew Stewart, Benjamin James Kerr
  • Patent number: 8654884
    Abstract: A method and circuit for performing channel equalization in a high speed transmission system comprising a transmitter and receiver. An application specific digital signal processor, ASDSP, performs channel equalization and compensation on digital data received from an analogue-to digital converter of the receiver. The ASDSP is operable to execute an application specific set of op-codes needed for performing channel equalization and compensation. An ASDSP register is coupled between the ASDSP and a system CPU in a feedback loop for performing channel equalization at the receiver. The ASDSP stores equalizer parameters and bit error rate measurements used by the ASDSP for performing channel equalization and compensation. An ASDSP program storage memory, coupled to and accessible by the ASDSP, stores an ASDSP micro-sequence program for controlling the processing steps for channel equalization and dataflow through the ASDSP.
    Type: Grant
    Filed: April 14, 2011
    Date of Patent: February 18, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Benjamin James Kerr
  • Publication number: 20120044983
    Abstract: A method and circuit for performing channel equalisation in a high speed transmission system comprising a transmitter and receiver. An application specific digital signal processor, ASDSP, performs channel equalisation and compensation on digital data received from an analogue-to digital converter of the receiver. The ASDSP is operable to execute an application specific set of op-codes needed for performing channel equalisation and compensation. An ASDSP register is coupled between the ASDSP and a system CPU in a feedback loop for performing channel equalisation at the receiver. The ASDSP stores equalizer parameters and bit error rate measurements used by the ASDSP for performing channel equalisation and compensation. An ASDSP program storage memory, coupled to and accessible by the ASDSP, stores an ASDSP micro-sequence program for controlling the processing steps for channel equalisation and dataflow through the ASDSP.
    Type: Application
    Filed: April 14, 2011
    Publication date: February 23, 2012
    Inventor: Benjamin James Kerr
  • Patent number: 7328043
    Abstract: There is disclosed a telephony apparatus comprising a base station and a handset, one of the base station and the handset being connected to a telephony system via an IEEE 802.11 interface, the base station and the handset each further being provided with a Bluetooth interface, speech data and/or control data being transmitted between the base station and the handset on the Bluetooth interface.
    Type: Grant
    Filed: August 9, 2005
    Date of Patent: February 5, 2008
    Assignee: Avaya ECS Ltd.
    Inventor: Benjamin James Kerr