Patents by Inventor Benjamin Vincent

Benjamin Vincent has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9171904
    Abstract: A FinFET device and a method for manufacturing a FinFET device is provided. An example device may comprise a substrate including at least two fin structures. Each of the at least two fin structures may be in contact with a source and drain region and each of the at least two fin structures may include a strain relaxed buffer (SRB) overlying and in contact with the substrate and an upper layer overlying and in contact with the SRB. The composition of the upper layer and the SRB may be selected such that the upper layer of a first fin structure is subjected to a first mobility enhancing strain in the as-grown state, the first mobility enhancing strain being applied in a longitudinal direction from the source region to the drain region and where at least an upper part of the upper layer of a second fin structure is strain-relaxed.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: October 27, 2015
    Assignee: IMEC
    Inventors: Geert Eneman, Benjamin Vincent, Voon Yew Thean
  • Publication number: 20150259298
    Abstract: The present invention provides novel compounds (e.g., compounds of Formula (I)), and pharmaceutically acceptable salts, solvates, hydrate, polymorphs, co-crystals, tautomers, stereoisomers, isotopically labeled derivatives, prodrugs, and compositions thereof. Also provided are methods and kits comprising the inventive compounds, or compositions thereof, for treating and/or preventing a fungal or protozoan infection, inhibiting the activity of a fungal or protozoan enzyme, killing a fungus or protozoan, or inhibiting the growth of a fungus or protozoan. The fungus may be a Candida species, Sacchawmyces species, or other pathogenic fungal species. The compounds of the invention may inhibit the activity of fungal or protozoan mitochondrial phosphate carrier protein.
    Type: Application
    Filed: October 16, 2013
    Publication date: September 17, 2015
    Applicants: Whitehead Institute for biomedical Research, Massachusetts Institute of Technology, The Broad Institute, Inc.
    Inventors: Benjamin Vincent, Luke Whitesell, Susan L. Lindquist, Willmen Youngsaye, Stephen L. Buchwald, Jean-Baptiste Langlois, Jun Pu, Benito Munoz, Sivaraman Dandapani
  • Patent number: 9117777
    Abstract: A method for reducing defects from an active layer is disclosed. The active layer may be part of a semiconductor in a semiconductor device. The active layer may be defined at least laterally by an isolation structure, and may physically contact an isolation structure at a contact interface. The isolation structure and the active layer may abut on a common substantially planar surface. The method may include providing a patterned stress-inducing layer on the common substantially planar surface. The stress-inducing layer may be adapted for inducing a stress field in the active layer, and induced stress field may result in a shear stress on a defect in the active layer. The method may also include performing an anneal step after providing the patterned stress-inducing layer on the common substantially planar surface. The method may additionally include removing the patterned stress-inducing layer from the common substantially planar surface.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: August 25, 2015
    Assignee: IMEC
    Inventors: Benjamin Vincent, Geert Eneman
  • Patent number: 9040391
    Abstract: The invention relates to a process for making at least one GeOI structure by germanium condensation of a SiGe layer supported by a layer of silicon oxide. The layer of silicon oxide is doped with germanium, the concentration of germanium in the layer of silicon oxide being such that it lowers the flow temperature of the layer of silicon oxide below the oxidation temperature allowing germanium condensation of the SiGe layer.
    Type: Grant
    Filed: August 12, 2009
    Date of Patent: May 26, 2015
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE
    Inventors: Jean-François Damlencourt, Benjamin Vincent
  • Patent number: 9029217
    Abstract: The disclosure is related to a band engineered semiconductor device comprising a substrate and a protruding structure that is formed in a recess in the substrate. The protruding structure extends above the recess and has a buried portion and an extended portion. At least the extended portion comprises a semiconductor material having an inverted ‘V’ band gap profile with a band gap value increasing gradually from a first value at lateral edges of the structure to a second value, higher than the first value, in a center of the structure. The disclosure is also related to the method of manufacturing of such a band engineered semiconductor device.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: May 12, 2015
    Assignees: IMEC, GlobalFoundries Inc.
    Inventors: Benjamin Vincent, Geert Hellings, David Paul Brunco
  • Publication number: 20150126010
    Abstract: The disclosure is related to a band engineered semiconductor device comprising a substrate and a protruding structure that is formed in a recess in the substrate. The protruding structure extends above the recess and has a buried portion and an extended portion. At least the extended portion comprises a semiconductor material having an inverted ‘V’ band gap profile with a band gap value increasing gradually from a first value at lateral edges of the structure to a second value, higher than the first value, in a center of the structure. The disclosure is also related to the method of manufacturing of such a band engineered semiconductor device.
    Type: Application
    Filed: January 8, 2015
    Publication date: May 7, 2015
    Applicants: GLOBALFOUNDRIES INC., IMEC
    Inventors: Benjamin Vincent, Geert Hellings, David Paul Brunco
  • Patent number: 8963225
    Abstract: The disclosure is related to a band engineered semiconductor device comprising a substrate, a protruding structure that is formed in a recess in the substrate and is extending above the recess having a buried portion and an extended portion, and wherein at least the extended portion comprises a semiconductor material having an inverted ‘V’ band gap profile with a band gap value increasing gradually from a first value at lateral edges of the structure to a second value, higher than the first value, in a center of the structure. The disclosure is also related to the method of manufacturing of such band engineered semiconductor device.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: February 24, 2015
    Assignees: IMEC, GLOBALFOUNDRIES Inc.
    Inventors: Benjamin Vincent, Geert Hellings, David Paul Brunco
  • Patent number: 8917854
    Abstract: A system, method, and device for forming contextualized competitions in a work environment are disclosed. The system includes a performance metric computation component which computes performance metrics, a visualization component which generates a visual interface for display to a supervisor, and a processor which implements the components. The method includes receiving information related to a set of agents operating in a work environment. A first aggregated value for a first performance metric and a second aggregated value for a second performance metric are computed. The first and second values are visualized, and a predicted effect on the second performance metric when the first performance metric is altered is visualized. The device serves as a decision-making support tool including a plurality of control mechanisms for altering at least one performance metric and displaying the predicted effect on another.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: December 23, 2014
    Assignee: Xerox Corporation
    Inventors: Stefania Castellani, Tommaso Colombino, Benjamin Vincent Hanrahan
  • Publication number: 20140192970
    Abstract: A system, method, and device for forming contextualized competitions in a work environment are disclosed. The system includes a performance metric computation component which computes performance metrics, a visualization component which generates a visual interface for display to a supervisor, and a processor which implements the components. The method includes receiving information related to a set of agents operating in a work environment. A first aggregated value for a first performance metric and a second aggregated value for a second performance metric are computed. The first and second values are visualized, and a predicted effect on the second performance metric when the first performance metric is altered is visualized. The device serves as a decision-making support tool including a plurality of control mechanisms for altering at least one performance metric and displaying the predicted effect on another.
    Type: Application
    Filed: January 8, 2013
    Publication date: July 10, 2014
    Applicant: XEROX CORPORATION
    Inventors: Stefania Castellani, Tommaso Colombino, Benjamin Vincent Hanrahan
  • Publication number: 20140170837
    Abstract: A method for reducing defects from an active layer is disclosed. The active layer may be part of a semiconductor in a semiconductor device. The active layer may be defined at least laterally by an isolation structure, and may physically contact an isolation structure at a contact interface. The isolation structure and the active layer may abut on a common substantially planar surface. The method may include providing a patterned stress-inducing layer on the common substantially planar surface. The stress-inducing layer may be adapted for inducing a stress field in the active layer, and induced stress field may result in a shear stress on a defect in the active layer. The method may also include performing an anneal step after providing the patterned stress-inducing layer on the common substantially planar surface. The method may additionally include removing the patterned stress-inducing layer from the common substantially planar surface.
    Type: Application
    Filed: December 13, 2013
    Publication date: June 19, 2014
    Applicant: IMEC
    Inventors: Benjamin Vincent, Geert Eneman
  • Publication number: 20140151766
    Abstract: A FinFET device and a method for manufacturing a FinFET device is provided. An example device may comprise a substrate including at least two fin structures. Each of the at least two fin structures may be in contact with a source and drain region and each of the at least two fin structures may include a strain relaxed buffer (SRB) overlying and in contact with the substrate and an upper layer overlying and in contact with the SRB. The composition of the upper layer and the SRB may be selected such that the upper layer of a first fin structure is subjected to a first mobility enhancing strain in the as-grown state, the first mobility enhancing strain being applied in a longitudinal direction from the source region to the drain region and where at least an upper part of the upper layer of a second fin structure is strain-relaxed.
    Type: Application
    Filed: November 21, 2013
    Publication date: June 5, 2014
    Applicant: IMEC
    Inventors: Geert Eneman, Benjamin Vincent, Voon Yew Thean
  • Patent number: 8709918
    Abstract: A method for selective deposition of semiconductor materials in semiconductor processing is disclosed. In some embodiments, the method includes providing a patterned substrate comprising a first region and a second region, where the first region comprises an exposed first semiconductor material and the second region comprise an exposed insulator material. The method further includes selectively providing a film of the second semiconductor material on the first semiconductor material of the first region by providing a precursor of a second semiconductor material, a carrier gas that is not reactive with chlorine compounds, and tin-tetrachloride (SnCl4). The tin-tetrachloride inhibits the deposition of the second semiconductor material on the insulator material of the second region.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: April 29, 2014
    Assignee: IMEC
    Inventors: Benjamin Vincent, Roger Loo, Matty Caymax
  • Publication number: 20140099774
    Abstract: Disclosed are methods for forming fins. In an example embodiment, a method includes providing a substrate that includes at least two elongated structures separated by an isolation region. Each elongated structure comprises a semiconductor alloy of a first semiconductor material and a second semiconductor material, and a relaxed portion of the elongated structure includes the semiconductor alloy in a relaxed and substantially defect-free condition. The method further includes subjecting the substrate to a condensation-oxidation, such that each elongated structure forms a fin and an oxide layer. The fin includes a fin base portion formed of the semiconductor alloy and a fin top portion of the first semiconductor material in a strained condition. The fin top portion is formed by condensation of the first semiconductor material. The oxide layer includes an oxide of the second semiconductor material. The method further includes removing at least some of the oxide layer.
    Type: Application
    Filed: October 7, 2013
    Publication date: April 10, 2014
    Applicant: IMEC
    Inventor: Benjamin Vincent
  • Publication number: 20140077332
    Abstract: The disclosure is related to a band engineered semiconductor device comprising a substrate, a protruding structure that is formed in a recess in the substrate and is extending above the recess having a buried portion and an extended portion, and wherein at least the extended portion comprises a semiconductor material having an inverted ‘V’ band gap profile with a band gap value increasing gradually from a first value at lateral edges of the structure to a second value, higher than the first value, in a center of the structure. The disclosure is also related to the method of manufacturing of such band engineered semiconductor device.
    Type: Application
    Filed: September 12, 2013
    Publication date: March 20, 2014
    Applicants: GLOBALFOUNDRIES Inc., IMEC
    Inventors: Benjamin Vincent, Geert Hellings, David Brunco
  • Patent number: 8656286
    Abstract: A system and method for providing mixed-initiative curation of information within a shared repository is provided. Static content is retrieved from a shared storage associated with a shared information management client. Dynamic content including one or more information items satisfying a similarity threshold with the static content is identified as similar dynamic content. An interactive visualization is generated within the shared information management client from information extracted from the static content and the similar dynamic content. The interactive visualization of the information is linked with the static content and the similar dynamic content. A selection of the information of the similar dynamic content is received from within the visualization. The static content in the shared storage is updated with the similar dynamic content linked with the selected information.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: February 18, 2014
    Assignees: Palo Alto Research Center Incorporated, Xerox Corporation
    Inventors: Gregorio Convertino, Ed H. Chi, Nicholas Chi-Yuen Kong, Benjamin Vincent Hanrahan, Guillaume Bouchard, Cedric Philippe C. J. G. Archambeau
  • Publication number: 20140020619
    Abstract: Disclosed are methods for growing Sn-containing semiconductor materials. In some embodiments, an example method includes providing a substrate in a chemical vapor deposition (CVD) reactor, and providing a semiconductor material precursor, a Sn precursor, and a carrier gas in the CVD reactor. The method further includes epitaxially growing a Sn-containing semiconductor material on the substrate, where the Sn precursor comprises tin tetrachloride (SnCl4). The semiconductor material precursor may be, for example, digermane, trigermane, higher-order germanium precursors, or a combination thereof. Alternatively, the semiconductor material precursor may be a silicon precursor.
    Type: Application
    Filed: March 29, 2012
    Publication date: January 23, 2014
    Inventors: Benjamin Vincent, Federica Gencarelli, Roger Loo, Matty Caymax
  • Publication number: 20140024204
    Abstract: Disclosed are methods for selective deposition of doped Group IV-Sn materials. In some embodiments, the method includes providing a patterned substrate comprising at least a first region and a second region, where the first region includes an exposed first semiconductor material and the second region includes an exposed insulator material, and performing at least two cycles of a grow-etch cyclic process. Each cycle includes depositing a doped Group IV-Tin (Sn) layer, where depositing the doped Group IV-Sn layer includes providing a Group IV precursor, a Sn precursor, and a dopant precursor, and using an etch gas to etch back the deposited doped Group IV-Sn layer.
    Type: Application
    Filed: July 17, 2013
    Publication date: January 23, 2014
    Applicant: IMECA
    Inventors: Andriy Hikavyy, Benjamin Vincent, Roger Loo
  • Patent number: 8569801
    Abstract: A three-dimensional CMOS circuit having at least a first N-conductivity field-effect transistor and a second P-conductivity field-effect transistor respectively formed on first and second crystalline substrates. The first field-effect transistor is oriented, in the first substrate, with a first secondary crystallographic orientation. The second field-effect transistor is oriented, in the second substrate, with a second secondary crystallographic orientation. The orientations of the first and second transistors form a different angle from the angle formed, in one of the substrates, by the first and second secondary crystallographic directions. The first and second substrates are assembled vertically.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: October 29, 2013
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventor: Benjamin Vincent
  • Publication number: 20130233238
    Abstract: Disclosed are methods and mask structures for epitaxially growing substantially defect-free semiconductor material. In some embodiments, the method may comprise providing a substrate comprising a first crystalline material, where the first crystalline material has a first lattice constant; providing a mask structure on the substrate, where the mask structure comprises a first level comprising a first opening extending through the first level (where a bottom of the first opening comprises the substrate), and a second level on top of the first level, where the second level comprises a plurality of second trenches positioned at a non-zero angle with respect to the first opening. The method may further comprise epitaxially growing a second crystalline material on the bottom of the first opening, where the second crystalline material has a second lattice constant different than the first lattice constant and defects in the second crystalline material are trapped in the first opening.
    Type: Application
    Filed: February 15, 2013
    Publication date: September 12, 2013
    Applicant: IMEC
    Inventors: Benjamin Vincent, Aaron Thean, Liesbeth Witters
  • Patent number: 8530339
    Abstract: The present disclosure is related to a method for the deposition of a continuous layer of germanium on a substrate by chemical vapor deposition. According to the disclosure, a mixture of a non-reactive carrier gas and a higher order germanium precursor gas, i.e. of higher order than germane (GeH4), is applied. In an example embodiment, the deposition is done under application of a deposition temperature between 275° C. and 500° C., with the partial pressure of the precursor gas within the mixture being at least 20 mTorr for temperatures between 275° C. and 285° C., and at least 10 mTorr for temperatures between 285° and 500° C.
    Type: Grant
    Filed: January 11, 2012
    Date of Patent: September 10, 2013
    Assignee: IMEC
    Inventors: Benjamin Vincent, Matty Caymax, Roger Loo, Johan Dekoster