Patents by Inventor Beom Ju Shin

Beom Ju Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Data storage device including controller for controlling nonvolatile memory devices
    Patent number: 9823853
    Abstract: A data storage device includes a first nonvolatile memory device including a target memory region, and a controller suitable for performing a first data input operation to transmit first data, which is to be stored in the target memory region, to the first nonvolatile memory device, regardless of whether a size of the first data corresponds to the target memory region.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: November 21, 2017
    Assignee: SK Hynix Inc.
    Inventor: Beom Ju Shin
  • DATA PROCESSING SYSTEM AND OPERATING METHOD OF DATA PROCESSING SYSTEM
    Publication number: 20170293430
    Abstract: A data processing system may include: a first memory system including a first memory device, and a first controller of the first memory device; and a second memory system including a second memory device, and a second controller of the second memory device, the first memory system may receive a command from a host, and then checks time information included in the command and performs a first update operation for the first memory device for a first time corresponding to the time information, and the second memory system may perform a second update operation for the second memory device for the first time for which the first update operation is performed.
    Type: Application
    Filed: September 20, 2016
    Publication date: October 12, 2017
    Inventor: Beom-Ju SHIN
  • MEMORY DEVICE AND OPERATING METHOD THEREOF
    Publication number: 20170277454
    Abstract: Provided herein are a memory device and an operating method thereof. The memory device includes: a memory device comprising: a memory cell array including a plurality of pages; a peripheral circuit suitable for successively receiving a plurality of logical page data, and performing a program operation with the received logical page data to a selected page; and a control logic suitable for controlling the peripheral circuit to perform, in parallel, the program operation to the selected page with reception-completed logical page data among the plurality of logical page data while receiving other logical page data.
    Type: Application
    Filed: August 23, 2016
    Publication date: September 28, 2017
    Inventor: Beom Ju SHIN
  • MEMORY SYSTEM AND OPERATING METHOD OF MEMORY SYSTEM
    Publication number: 20170277476
    Abstract: A memory system may include: a memory device comprising a plurality of pages, which include a plurality of memory cells coupled to a plurality of word lines, and in which data is stored, and a plurality of memory blocks in which the pages are included; and a controller configured to divide the memory blocks into a first group and a second group, perform a command operation corresponding to a command received from a host, and respectively store segments of user data and meta data for the command operation in memory blocks included in the first group or memory blocks included in the second group, in accordance with type information of the user data Included in the command.
    Type: Application
    Filed: September 15, 2016
    Publication date: September 28, 2017
    Inventor: Beom-Ju SHIN
  • DATA PROCESSING SYSTEM INCLUDING DATA STORAGE DEVICE
    Publication number: 20170277474
    Abstract: A data processing system includes a data storage device; and a host device configured to transmit a write request to the data storage device to store data in the data storage device, wherein the host device transmits the write request including a request purpose meaning what a cause that results in the write request is, and wherein the data storage device processes the write request based on the request purpose.
    Type: Application
    Filed: July 22, 2016
    Publication date: September 28, 2017
    Inventor: Beom Ju SHIN
  • MEMORY SYSTEM AND OPERATING METHOD THEREOF
    Publication number: 20170270040
    Abstract: There are provided a memory system having improved operation speed and an operating method thereof. A method of operating a controller for controlling a memory block including a plurality of pages includes determining whether the memory block is in an open state or a closed state, if the memory block is in the open state, reading merged metadata included in the plurality of pages, and rebuilding logical to physical (L2P) mapping data of a plurality of logical pages included in each of the plurality of pages based on the merged metadata.
    Type: Application
    Filed: August 15, 2016
    Publication date: September 21, 2017
    Inventors: Beom Ju SHIN, Dae Hong KIM
  • DATA STORAGE DEVICE
    Publication number: 20170269833
    Abstract: A data storage device includes a first nonvolatile memory device including a target memory region, and a controller suitable for performing a first data input operation to transmit first data, which is to be stored in the target memory region, to the first nonvolatile memory device, regardless of whether a size of the first data corresponds to the target memory region.
    Type: Application
    Filed: July 22, 2016
    Publication date: September 21, 2017
    Inventor: Beom Ju SHIN
  • MEMORY SYSTEM AND OPERATION METHOD THEREOF
    Publication number: 20170235487
    Abstract: A memory device includes: a memory including a plurality of blocks, each including a plurality of pages; and a control logic that controls a read operation and a copy-back operation on the memory based on a combination of a block read operation number and a page read operation number.
    Type: Application
    Filed: July 26, 2016
    Publication date: August 17, 2017
    Inventor: Beom-Ju SHIN
  • Operating method of semiconductor memory device
    Patent number: 9728234
    Abstract: A method for operating a semiconductor memory device includes receiving input/output signals including a command, an address and data, through input/output lines; and receiving a first control signal and a second control signal, wherein, regardless of a state of the second control signal, when the first control signal which is enabled is received, the input/output signals received through the input/output lines are recognized as the command.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: August 8, 2017
    Assignee: SK Hynix Inc.
    Inventors: Do Hyun Kim, Beom Ju Shin
  • MEMORY SYSTEM AND OPERATING METHOD OF MEMORY SYSTEM
    Publication number: 20170206007
    Abstract: This technology relates to a memory system for processing data into a memory device and an operating method of the memory system. The memory system may include a memory device; and a controller suitable for: performing a command operation to the memory device in response to a command, calculating a foreground operation workload corresponding to the command, calculating a memory available workload of the memory device for the command operation, and dynamically determining priority and workload for the command operation based on the foreground operation workload and the memory available workload.
    Type: Application
    Filed: June 24, 2016
    Publication date: July 20, 2017
    Inventor: Beom-Ju SHIN
  • MEMORY DEVICE AND METHOD OF OPERATING THE SAME
    Publication number: 20170206037
    Abstract: Disclosed herein is a memory system including: a plurality of memory chips coupled to a plurality of input/output lines included in a channel and output ready/busy signals to the input/output lines in response to a status check command; and a memory controller configured to transmit the status check command to the memory chips through the channel and simultaneously determine an operation status of the memory chips depending on the ready/busy signals received through the input/output lines.
    Type: Application
    Filed: June 15, 2016
    Publication date: July 20, 2017
    Inventor: Beom Ju SHIN
  • Data storage device and the operating method thereof
    Patent number: 9659638
    Abstract: A data storage device includes a nonvolatile memory device including a first plane and a second plane; and a controller configured to provide a read command for reading simultaneously the first plane and the second plane, a first address for accessing the first plane and a second address for accessing the second plane, to the nonvolatile memory device, wherein the nonvolatile memory device reads all page types that should be read from the first plane and the second plane, from each of the first plane and the second plane, according to the read command, the first address and the second address.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: May 23, 2017
    Assignee: SK Hynix Inc.
    Inventor: Beom Ju Shin
  • Memory system
    Patent number: 9442797
    Abstract: A memory system is provided. The memory system includes a memory device suitable for reading out data from memory cells by a plurality of read voltages having various levels, and a controller suitable for updating probabilistic information based on the read out data when the read out data is input to the controller, and performing an error correction operation by the updated probabilistic information, wherein the controller updates the probabilistic information a predetermined number of times that the memory device reads out the data.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: September 13, 2016
    Assignee: SK Hynix Inc.
    Inventor: Beom Ju Shin
  • APPARATUS FOR INFERRING PEDESTRIAN POSITION BASED ON PEDESTRIAN MOVEMENT DETECTION, AND METHOD THEREFOR
    Publication number: 20150308831
    Abstract: Disclosed are an apparatus for estimating a pedestrian position based on pedestrian motion recognition, and a method therefor. The method for estimating the pedestrian position based on pedestrian motion recognition includes recognizing a specific motion of a plurality of motions of the pedestrian, performing a unique pedestrian dead-reckoning (PDR) technique corresponding to the recognized specific motion among unique PDR techniques for each of the plurality of motions of the pedestrian, and estimating the pedestrian's position by the performed unique PDR technique.
    Type: Application
    Filed: September 12, 2013
    Publication date: October 29, 2015
    Inventors: Taik Jin LEE, Seok LEE, Sun Ho KIM, Jae Hun KIM, Beom Ju SHIN, Chul Ki KIM, Young Min JHON
  • MEMORY SYSTEM
    Publication number: 20150178156
    Abstract: A memory system is provided. The memory system includes a memory device suitable for reading out data from memory cells by a plurality of read voltages having various levels, and a controller suitable for updating probabilistic information based on the read out data when the read out data is input to the controller, and performing an error correction operation by the updated probabilistic information, wherein the controller updates the probabilistic information a predetermined number of times that the memory device reads out the data.
    Type: Application
    Filed: May 21, 2014
    Publication date: June 25, 2015
    Applicant: SK hynix Inc.
    Inventor: Beom Ju SHIN
  • Multi-chip package and method of operating the same
    Patent number: 8644092
    Abstract: A semiconductor memory device includes a memory cell array including first memory cells for storing data and second memory cells for storing chip identification (ID) information, a data comparison circuit configured to compare input data and the stored data of the first memory cells and to output comparison data, and output circuits configured to output the comparison data received in parallel from the data comparison circuit. The comparison data is outputted through a selected one of the output circuits according to an enable signal generated based on the chip ID information.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: February 4, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kyoung Nam Kim, Beom Ju Shin
  • Internal signal generator for use in semiconductor memory device
    Patent number: 8483005
    Abstract: A semiconductor memory device includes a pipe latch unit having a plurality of pipe latches, each of which latches an external address in response to the activation of an external command and outputs an internal address in response to the activation of an internal command corresponding to the external command. A pipe latch control unit is configured to control the pipe latch unit to sequentially enable the plurality of pipe latches. An output drive unit is configured to selectively output the internal address or the external address. The internal command is activated after a predetermined latency from an activation timing of the external command.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: July 9, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Beom-Ju Shin
  • Nonvolatile memory apparatus and method for processing configuration information thereof
    Patent number: 8437203
    Abstract: A nonvolatile memory apparatus includes a memory device having a configuration information storage block for storing a first configuration data group and a second configuration data group having fewer bits than the first configuration data group and a configuration information processing circuit configured to determine a majority of the first configuration data group outputted from the memory device, during a first period of a power-up operation, and determine a majority of the second configuration data group outputted from the memory device, during a second period after the first period.
    Type: Grant
    Filed: December 31, 2010
    Date of Patent: May 7, 2013
    Assignee: SK Hynix Inc.
    Inventors: Kyoung Nam Kim, Beom Ju Shin
  • Multi-chip package
    Patent number: 8344754
    Abstract: A multi-chip package includes a plurality of chips coupled in parallel to an I/O pad and an output driver circuit included in each of the chips and configured to transmit output data to the I/O pad. The driving force of the output driver circuit is controlled on the basis of stack information indicative of the number of chips being activated.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: January 1, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kyoung Nam Kim, Beom Ju Shin
  • Semiconductor memory device having capability of stable initial operation
    Patent number: 8347198
    Abstract: A semiconductor memory device is capable of outputting a preset logic level through an EDC pin according to an operation mode during an initial operation, and providing a stable operation according to the specification of the semiconductor memory device just after the input of a data clock (WCK). The semiconductor memory device includes an output circuit configured to output a synchronous data in response to a data clock when the data clock is enabled, and output an asynchronous data when the data clock is disabled, and a data clock detection circuit configured to control outputting the asynchronous data by checking whether the data clock is in a stable state or not.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: January 1, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Beom-Ju Shin, Sang-Sic Yoon