Patents by Inventor Beom-Taek Lee
Beom-Taek Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11921309Abstract: A polarizing plate and an optical display including the same are provided. A polarizing plate includes: a polarizer; and a first protective layer and a second protective layer sequentially stacked on a surface of the polarizer, and the second protective layer includes a positive C retardation layer, the positive C retardation layer having a thickness of about 10 ?m or less, an index of refraction of about 1.50 to about 1.55, and a glass transition temperature (Tg) of about 150° C. to about 250° C.Type: GrantFiled: September 17, 2021Date of Patent: March 5, 2024Assignee: Samsung SDI Co., Ltd.Inventors: A Ra Jo, Beom Deok Lee, Seon Gyeong Jeong, Seong Hoon Lee, Seung Mi Shin, Wan Taek Hong
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Patent number: 11233348Abstract: A connector includes a connector housing forming a receptacle configured to receive an add-in card. The connector further includes a first connector pin configured to electrically couple to the add-in card responsive to the add-in card being inserted into the receptacle. The first connector pin extends from the connector housing to contact a first solder pad disposed on a printed circuit board (PCB). The connector further includes a second connector pin configured to electrically couple to the add-in card responsive to the add-in card being inserted into the receptacle. The second connector pin extends from the connector housing to contact a second solder pad disposed on the PCB. The first connector pin is oriented toward the second connector pin to couple to the PCB in a toe-routing configuration and the second connector pin is oriented away from the first connector pin to couple to the PCB in the toe-routing configuration.Type: GrantFiled: April 24, 2020Date of Patent: January 25, 2022Assignee: Intel CorporationInventors: Se-Jung Moon, Chien-Ping Kao, Gaudencio Hernandez Sosa, Beom-Taek Lee
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Publication number: 20210399764Abstract: An apparatus comprises a crosstalk cancelation circuit comprising a plurality of taps to output signals based on a signal transmitted via a first data line; and a summation circuit to combine a signal received by a second data line with the signals output by the plurality of taps to reduce near-end crosstalk present in the signal received by the second data line.Type: ApplicationFiled: September 1, 2021Publication date: December 23, 2021Applicant: Intel CorporationInventors: Jingbo Li, Beom-Taek Lee, Jong-Ru Guo, Yunhui Chu, Chunfei Ye, Kai Xiao
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Publication number: 20210289617Abstract: Methods and apparatus to facilitate routing of high-speed data channels are described herein. Under one aspect, a high-speed data channel is routed between an integrated circuit (IC) and a high-speed data connector mounted to a multilayer printed circuit board as part of a circuit assembly. The circuit assembly includes a signal pathway providing a high-speed data channel from the integrated circuit to the high-speed data connector, wherein a portion of the signal pathway includes an axial cable, such as a twin axial cable. The high-speed data channel may comprise a multi-lane data channel and may be bi-directional.Type: ApplicationFiled: May 28, 2021Publication date: September 16, 2021Inventors: Richard I. MELLITZ, Brandon GORE, Beom-Taek LEE
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Publication number: 20210159625Abstract: A connector includes a connector housing forming a receptacle configured to receive an add-in card. The connector further includes a first connector pin configured to electrically couple to the add-in card responsive to the add-in card being inserted into the receptacle. The first connector pin extends from the connector housing to contact a first solder pad disposed on a printed circuit board (PCB). The connector further includes a second connector pin configured to electrically couple to the add-in card responsive to the add-in card being inserted into the receptacle. The second connector pin extends from the connector housing to contact a second solder pad disposed on the PCB. The first connector pin is oriented toward the second connector pin to couple to the PCB in a toe-routing configuration and the second connector pin is oriented away from the first connector pin to couple to the PCB in the toe-routing configuration.Type: ApplicationFiled: April 24, 2020Publication date: May 27, 2021Inventors: Se-Jung MOON, Chien-Ping KAO, Gaudencio HERNANDEZ SOSA, Beom-Taek LEE
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Publication number: 20200083155Abstract: Apparatuses, systems and methods associated with electrical routing layout of printed circuit boards and integrated circuit substrates are disclosed herein. In embodiments, an apparatus includes a first electrically conductive path that extends through a region, wherein the first electrically conductive path includes a first pad located at a surface of the region, a first via that extends through the region, and a first trace that extends in a first direction. The apparatus further includes a second electrically conductive path that extends through the region, wherein the second electrically conductive path includes a second pad located at the surface and adjacent to the first pad, a second via that extends through the region, and a second trace that extends in a second direction. Other embodiments may be described and/or claimed.Type: ApplicationFiled: September 11, 2018Publication date: March 12, 2020Inventors: Raul ENRIQUEZ SHIBAYAMA, Vijaya BODDU, Luis Nathan PEREZ ACOSTA, Francisco Javier GALARZA MEDINA, Kai XIAO, Luis ROSALES-GALVAN, Beom-Taek LEE, Carlos Alberto LIZALDE MORENO, Gaudencio HERNANDEZ SOSA, Mo LIU
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Patent number: 10477684Abstract: Techniques and mechanisms for facilitating connection between a packaged device and a substrate of another device. In an embodiment, a device—such as a printed circuit board—comprises a substrate and a hardware interface at a first side of the substrate, the hardware interface to couple the device to a package including integrated circuitry. The device is further configured to couple to a bridge device via contacts disposed at a second side of the substrate. An interconnect extends from the hardware interface to one of the contacts at the second side. In another embodiment, coupling the substrate to the bridge device interconnects two of the contacts at the second side to one another via the bridge device, where one or more contacts of the hardware interface (e.g., only a subset of all such contacts) are also interconnected with the bridge device via the second side.Type: GrantFiled: September 25, 2015Date of Patent: November 12, 2019Assignee: Intel CorporationInventors: Raul Enriquez Shibayama, Beom-Taek Lee, Carolina Garcia Robles
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Publication number: 20190200450Abstract: Methods and apparatus for utilizing flexible (flex) circuit technology and/or axial cable to facilitate routing of high-speed data channels are described herein. Under one aspect, a high-speed data channel if routed between an integrated circuit (IC) and a high-speed data connector mounted to a multilayer printed circuit board as part of a circuit assembly. The circuit assembly includes a signal pathway providing a high-speed data channel from the integrated circuit to the high-speed data connector, wherein a portion of the signal pathway includes a flex circuit or axial cable.Type: ApplicationFiled: September 19, 2017Publication date: June 27, 2019Applicant: Intel CorporationInventors: Richard I. MELLITZ, Brandon GORE, Beom-Taek LEE
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Patent number: 10249924Abstract: Techniques and mechanisms to provide a compact arrangement of vias extending through at least a portion of a printed circuit board (PCB) or other substrate. In an embodiment, the substrate includes a dielectric material and a sidewall structure forming a hole region that extends at least partially through the dielectric material. The hole region adjoins each of a first via and a second via, and is also located between the first via and second via. In another embodiment, the first via is coupled to exchange a first signal of a differential signal pair, and the second via is coupled to exchange a second signal of the same differential signal pair.Type: GrantFiled: June 26, 2015Date of Patent: April 2, 2019Assignee: INTEL CORPORATIONInventors: Kai Xiao, Raul Enriquez Shibayama, Gong Ouyang, Jose Diego Guillen Gonzalez, Beom-Taek Lee
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Publication number: 20190044286Abstract: In accordance with embodiments disclosed herein, there is provided a ground bar as a robust grounding scheme for a high-speed connector design. A connector includes a housing and a first signal pin, first and second ground pins, and a ground bar disposed within the housing. The housing includes a first receptacle through which a first circuit board is inserted. Responsive to the first circuit board being inserted into the first receptacle, the first signal pin is to contact a first contact electrode on the first circuit board, the first ground pin is to contact a first ground contact electrode on the first circuit board, and the second ground pin is to contact a second ground contact electrode on the first circuit board. The ground bar is connected between a first connection point of the first ground pin and a second connection point of the second ground pin.Type: ApplicationFiled: September 18, 2018Publication date: February 7, 2019Inventors: Se-Jung MOON, Hansel DSILVA, Beom-Taek LEE
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Patent number: 9954332Abstract: Apparatuses and processes associated with a dual in-line memory module (DIMM) adaptor card. Specifically, the DIMM adaptor card may be configured to removeably couple with a slot of a printed circuit board (PCB). The DIMM adaptor card may further be configured to removeably couple with a first DIMM and a second DIMM. Other embodiments may be described and/or claimed.Type: GrantFiled: June 13, 2017Date of Patent: April 24, 2018Assignee: Intel CorporationInventors: Shaowu Huang, Beom-Taek Lee
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Patent number: 9935036Abstract: Some embodiments of the present disclosure describe an integrated circuit (IC) package assembly having first, second, and third insulated wires wire bonded with die pads on an IC die, with an outer surface of the second insulated wire located at a distance of less than an outer cross-sectional diameter of the second insulated wire from an outer surface of the first insulated wire at a first location and located at a distance of less than the outer cross-sectional diameter from an outer surface of the third insulated wire at a second location. Other embodiments may be described and/or claimed.Type: GrantFiled: June 26, 2015Date of Patent: April 3, 2018Assignee: Intel CorporationInventors: Gong Ouyang, Beom-Taek Lee
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Patent number: 9924595Abstract: In one embodiment, the apparatus comprises: a substrate having a first side and a second side, the second side being on an opposite side of the substrate from the first side, where the substrate has a first location on the first side at which an semiconductor package is to be coupled; and a cable coupled to the substrate on the second side of the substrate at a second location on the second side, the second location being at least partially below the first location.Type: GrantFiled: December 11, 2014Date of Patent: March 20, 2018Assignee: INTEL CORPORATIONInventors: Beom-Taek Lee, Raul Enriquez Shibayama
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Patent number: 9894752Abstract: Systems, apparatuses, and methods may include a circuit board having a plated through hole with a via portion and a stub portion and a self-coupled inductor electrically coupled to the via portion of the plated through hole. The self-coupled inductor may include a first inductor mutually coupled to a second inductor in series to reduce a capacitive effect of the stub portion of the plated through hole.Type: GrantFiled: April 3, 2015Date of Patent: February 13, 2018Assignee: Intel CorporationInventors: Zhichao Zhang, Gong Ouyang, Kai Xiao, Kemal Aygun, Beom-Taek Lee
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Patent number: 9806392Abstract: Apparatuses and methods associated with shield lines, and/or complementary decoupling capacitors and/or electromagnetic absorbing materials are disclosed herein. In embodiments, an apparatus may include a substrate having a ground plane; and a first and a second transmission line disposed on the substrate. Further, the apparatus may include a shield line constituted with electromagnetic absorbing material disposed between the first and second transmission lines and not coupled with the ground plane. In embodiments, the substrate may further include a power plane having a plurality of edges and a plurality of spacing; a plurality of decoupling capacitors disposed on the power or ground plane; and electromagnetic absorbing materials adhered to the plurality of edges and disposed in the plurality of spacing. Other embodiments may be described and/or claimed.Type: GrantFiled: May 19, 2015Date of Patent: October 31, 2017Assignee: Intel CorporationInventors: Shaowu Huang, Hanqiao Zhang, Kai Xiao, Beom-Taek Lee, John J. Abbott, Gary Charles
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Publication number: 20170309570Abstract: The present disclosure is directed to a reconfigurable repeater system. A system may comprise a PCB to which devices are coupled. At least one communication channel may convey communications signals between the devices. At least one receptacle may also be coupled to the PCB and may intersect the at least one communication channel so as to separate the at least one communication channel into sections. Inserting at least one extender module into the at least one receptacle may couple the at least one extender module to the sections of the communication module. The at least one extender module may include at least one conductor to convey communication signals between the sections of the at least one communication channel. Another configuration of the at least one extender module may include a repeater to receive, amplify and transmit communication signals between the sections of the at least one communication channel.Type: ApplicationFiled: June 12, 2017Publication date: October 26, 2017Applicant: Intel CorporationInventors: SHAOWU HUANG, BEOM-TAEK Lee
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Publication number: 20170295647Abstract: Apparatuses and processes associated with a dual in-line memory module (DIMM) adaptor card. Specifically, the DIMM adaptor card may be configured to removeably couple with a slot of a printed circuit board (PCB). The DIMM adaptor card may further be configured to removeably couple with a first DIMM and a second DIMM. Other embodiments may be described and/or claimed.Type: ApplicationFiled: June 13, 2017Publication date: October 12, 2017Inventors: Shaowu Huang, Beom-Taek Lee
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Patent number: 9750129Abstract: Embodiments of the present disclosure are directed toward techniques and configurations for electrical signal absorption in an interconnect disposed in a printed circuit board (PCB) assembly. In one instance, a PCB assembly may comprise a substrate, and an interconnect formed in the substrate to route an electrical signal within the PCB. The interconnect may be coupled with a connecting component that is disposed on a surface of the PCB. An absorbing material may be disposed on the PCB to be in direct contact with at least a portion of the connecting component to at least partially absorb a portion of the electrical signal. Other embodiments may be described and/or claimed.Type: GrantFiled: September 14, 2016Date of Patent: August 29, 2017Assignee: Intel CorporationInventors: Shaowu Huang, Kai Xiao, Beom-Taek Lee, Boping Wu, Xiaoning Ye
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Patent number: 9716361Abstract: Apparatuses and processes associated with a dual in-line memory module (DIMM) adaptor card. Specifically, the DIMM adaptor card may be configured to removeably couple with a slot of a printed circuit board (PCB). The DIMM adaptor card may further be configured to removeably couple with a first DIMM and a second DIMM. Other embodiments may be described and/or claimed.Type: GrantFiled: October 12, 2016Date of Patent: July 25, 2017Assignee: Intel CorporationInventors: Shaowu Huang, Beom-Taek Lee
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Publication number: 20170207146Abstract: Some embodiments of the present disclosure describe an integrated circuit (IC) package assembly having first, second, and third insulated wires wire bonded with die pads on an IC die, with an outer surface of the second insulated wire located at a distance of less than an outer cross-sectional diameter of the second insulated wire from an outer surface of the first insulated wire at a first location and located at a distance of less than the outer cross-sectional diameter from an outer surface of the third insulated wire at a second location. Other embodiments may be described and/or claimed.Type: ApplicationFiled: June 26, 2015Publication date: July 20, 2017Inventors: GONG OUYANG, BEOM-TAEK LEE