Abstract: Implementation of a device with stacked transistors comprising: a first transistor of a first type, in particular N or P, the first transistor having a channel formed in one or more first semi-conducting rods of a semi-conducting structure including semi-conducting rods disposed above each other and aligned with each other, a second transistor of a second type, in particular P or N, with a gate-surrounding gate and a channel region formed in one or more second semi-conducting rods of said semi-conducting structure and disposed above the first semi-conducting rods, the source block of the second transistor being distinct from the source and drain block of the second transistor, the drain block of the second transistor being distinct from the drain and source blocks of the second transistor.

Abstract: Implementation of a device with stacked transistors comprising: a first transistor of a first type, in particular N or P, the first transistor having a channel formed in one or more first semi-conducting rods of a semi-conducting structure including semi-conducting rods disposed above each other and aligned with each other, a second transistor of a second type, in particular P or N, with a gate-surrounding gate and a channel region formed in one or more second semi-conducting rods of said semi-conducting structure and disposed above the first semi-conducting rods, the source block of the second transistor being distinct from the source and drain block of the second transistor, the drain block of the second transistor being distinct from the drain and source blocks of the second transistor.

Abstract: Implementation of a device with stacked transistors comprising: a first transistor of a first type, in particular N or P, the first transistor having a channel formed in one or more first semi-conducting rods of a semi-conducting structure including semi-conducting rods disposed above each other and aligned with each other, a second transistor of a second type, in particular P or N, with a gate-surrounding gate and a channel region formed in one or more second semi-conducting rods of said semi-conducting structure and disposed above the first semi-conducting rods, the source block of the second transistor being distinct from the source and drain block of the second transistor, the drain block of the second transistor being distinct from the drain and source blocks of the second transistor.

Abstract: A SOI substrate is covered by a semiconductor material pattern which includes a dividing pattern made from electrically insulating material. The dividing pattern is coated by one or more semiconductor materials. The semiconductor material pattern is covered by a gate electrode which is facing the dividing pattern. The semiconductor material pattern and the gate pattern are covered by a cap layer. The substrate is eliminated to access the source/drain regions. Two delineation patterns are formed to cover the source region and drain region and to leave the dividing pattern free. A second cap layer is deposited and access vias are formed to access the source/drain regions by elimination of the delineation patterns.

Abstract: A method for making connection elements between two different levels of components in a 3D integrated circuit, including: forming a lateral insulating area supported on at least one given conducting area among several interconnection areas on a first level of components, the insulating area extending around a semiconducting layer on a second level in which at least one transistor can be formed; removing a first portion of the lateral insulating area so as to form at least one hole exposing said given conducting area; and depositing a conducting material in the hole so as to form a first electrical connection element between the second component and the given conducting area.

Abstract: A method for making a three-dimensional integrated electronic circuit is provided, including making a first electrically conductive portion on a first dielectric layer covering a first semiconductor layer; then making a second dielectric layer covering the first electrically conductive portion such that it is disposed between the first and second dielectric layers, and a second semiconductor layer disposed on the second dielectric layer; then making a first electronic component in the second semiconductor layer, and a second electronic component in the first semiconductor layer; then making an electrical interconnection electrically linking the first and second electronic components together, of which a first part passes through the first dielectric layer and electrically connects the second electronic component to the first electrically conductive portion and of which a second part passes through a part of the second dielectric layer and electrically connects the first electronic component to the first elect

Abstract: Method for making connection elements between two different levels of components in a 3D integrated circuit including steps of: forming a lateral insulating area supported on at least one given conducting area among several interconnection areas on a first level of components, the insulating area extending around a semiconducting layer on a second level in which at least one transistor can be formed, removing a first portion of the lateral insulating area so as to form a first hole exposing said given conducting area; deposit a conducting material in the hole so as to form a first electrical connection element between the second component and said given conducting area.

Abstract: A SOI substrate is covered by a semiconductor material pattern which includes a dividing pattern made from electrically insulating material. The dividing pattern is coated by one or more semiconductor materials. The semiconductor material pattern is covered by a gate electrode which is facing the dividing pattern. The semiconductor material pattern and the gate pattern are covered by a cap layer. The substrate is eliminated to access the source/drain regions. Two delineation patterns are formed to cover the source region and drain region and to leave the dividing pattern free. A second cap layer is deposited and access vias are formed to access the source/drain regions by elimination of the delineation patterns.

Abstract: A SOI substrate is covered by a semiconductor material pattern which comprises a dividing pattern made from electrically insulating material. The dividing pattern is coated by one or more semiconductor materials. The semiconductor material pattern is covered by a gate electrode which faces the dividing pattern. The semiconductor material pattern and the gate pattern are covered by a covering layer. The substrate is eliminated to access the source/drain regions. A second covering layer is deposited and access vias are formed to access the source/drain regions and gate electrode.

Abstract: A method for making a three-dimensional integrated electronic circuit comprising steps for: making a first electrically conductive portion on a first dielectric layer covering a first semiconductor layer; then making a second dielectric layer covering the first electrically conductive portion such that the first electrically conductive portion is arranged between the first and second dielectric layers, and a second semiconductor layer arranged on the second dielectric layer; then making a first electronic component in the second semiconductor layer, and a second electronic component in the first semiconductor layer; then making an electrical interconnection electrically linking the first and second electronic components together, of which a first part passes through the first dielectric layer and electrically connects the second electronic component to the first electrically conductive portion and of which a second part passes through a part of the second dielectric layer and electrically connects the firs

Abstract: A SOI substrate is covered by a semiconductor material pattern which comprises a dividing pattern made from electrically insulating material. The dividing pattern is coated by one or more semiconductor materials. The semiconductor material pattern is covered by a gate electrode which faces the dividing pattern. The semiconductor material pattern and the gate pattern are covered by a covering layer. The substrate is eliminated to access the source/drain regions. A second covering layer is deposited and access vias are formed to access the source/drain regions and gate electrode.

Abstract: A method for making a microelectronic device with transistors, in which silicided source and drain zones are formed to apply a compressive strain on the channel, in some transistors.

Abstract: The method for producing a substrate provided with protection of its edges has a first step which is providing a substrate having a semiconductor material base. The substrate has opposite first and second main surfaces connected by a lateral surface. A first layer made from first protective material is then formed so as to coat the substrate. The first protective material is then etched on the lateral surface leaving a pattern of first protective material at least partially covering each of the first and second surfaces, and a second protective layer made from second protective material is then formed on the lateral surface devoid of the first protective material. After formation of the second protective layer, the first protective material is eliminated from the substrate.

Abstract: Method of producing an integrated electronic circuit comprising at least the steps of: producing a substrate comprising at least a first and second layer of semiconductor between which at least a third layer of material is placed, then producing at least a first MOS device, an active area of which is formed in at least part of the first layer of semiconductor, then producing at least a second MOS device, an active area of which is formed in at least part of the second layer of semiconductor, the active area of the second MOS device being placed between a gate of the second MOS device and the active area of the first MOS device.

Abstract: A method of producing a microelectronic device with transistors wherein a strain layer is formed on a series of transistors and the strain exerted on at least one given transistor of said series is released by removing a sacrificial layer situated between said given transistor and said strain layer.

Abstract: A method of producing a microelectronic device with transistors wherein a strain layer is formed on a series of transistors and the strain exerted on at least one given transistor of said series is released by removing a sacrificial layer situated between said given transistor and said strain layer.

Abstract: A method for making a microelectronic device with transistors, in which silicided source and drain zones are formed to apply a compressive strain on the channel, in some transistors.

Abstract: Method of producing an integrated electronic circuit comprising at least the steps of: producing a substrate comprising at least a first and second layer of semiconductor between which at least a third layer of material is placed, then producing at least a first MOS device, an active area of which is formed in at least part of the first layer of semiconductor, then producing at least a second MOS device, an active area of which is formed in at least part of the second layer of semiconductor, the active area of the second MOS device being placed between a gate of the second MOS device and the active area of the first MOS device.

Abstract: A method including: making a structure on a substrate, said structure comprising at least a portion of a semiconductor material forming a channel of a field effect transistor, a gate located on the channel; forming at least one dielectric portion completely covering said structure and zones of the substrate corresponding to locations of a source and a drain of the field effect transistor; making two holes in the dielectric portion on each side of said structure, such that the locations of the source and the drain form bottom walls of the two holes and sides of the channel are exposed; depositing a first metallic layer on at least the bottom walls of the two holes, at least covering said sides of the channel; and depositing a second metallic layer on the first metallic layer-to form the source and the drain of the field effect transistor.

Abstract: A method for producing a transistor with metallic source and drain including the steps of: a) producing a gate stack, b) producing two portions of a material capable of being selectively etched relative to a second dielectric material and arranged at the locations of the source and of the drain of the transistor, c) producing a second dielectric material-based layer covering the stack and the two portions of material, d) producing two holes in the second dielectric material-based layer forming accesses to the two portions of material, e) etching of said two portions of material, f) depositing a metallic material in the two formed cavities, and also including, between steps a) and b), a step of deposition of a barrier layer on the stack, against the lateral sides of the stack and against the face of the first dielectric material-based layer.