Patents by Inventor Bernard van Heck

Bernard van Heck has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220299551
    Abstract: A method to evaluate a semiconductor-superconductor heterojunction for use in a qubit register of a topological quantum computer includes (a) measuring one or both of a radio-frequency (RF) junction admittance of the semiconductor-superconductor heterojunction and a sub-RF conductance including a non-local conductance of the semiconductor-superconductor heterojunction, to obtain mapping data and refinement data; (b) finding by analysis of the mapping data one or more regions of a parameter space consistent with an unbroken topological phase of the semiconductor-superconductor heterojunction; and (c) finding by analysis of the refinement data a boundary of the unbroken topological phase in the parameter space and a topological gap of the semiconductor-superconductor heterojunction for at least one of the one or more regions of the parameter space.
    Type: Application
    Filed: February 15, 2022
    Publication date: September 22, 2022
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Dmitry PIKULIN, Mason L THOMAS, Chetan Vasudeo NAYAK, Roman Mykolayovych LUTCHYN, Bas NIJHOLT, Bernard VAN HECK, Esteban Adrian MARTINEZ, Georg Wolfgang WINKLER, Gijsbertus DE LANGE, John David WATSON, Sebastian HEEDT, Torsten KARZIG
  • Patent number: 11151470
    Abstract: A method to evaluate a semiconductor-superconductor heterojunction for use in a qubit register of a topological quantum computer includes measuring a radio-frequency (RF) junction admittance of the semiconductor-superconductor heterojunction to obtain mapping data; finding by analysis of the mapping data one or more regions of a parameter space consistent with an unbroken topological phase of the semiconductor-superconductor heterojunction; measuring a sub-RF conductance including a non-local conductance of the semiconductor-superconductor heterojunction in each of the one or more regions of the parameter space, to obtain refinement data; and finding by analysis of the refinement data a boundary of the unbroken topological phase in the parameter space and a topological gap of the semiconductor-superconductor heterojunction for at least one of the one or more regions of the parameter space.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: October 19, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Dmitry Pikulin, Mason L Thomas, Chetan Vasudeo Nayak, Roman Mykolayovych Lutchyn, Georg Wolfgang Winkler, Sebastian Heedt, Gijsbertus De Lange, Bernard Van Heck, Esteban Adrian Martinez, Lucas Casparis, Torsten Karzig
  • Publication number: 20210279626
    Abstract: A method to evaluate a semiconductor-superconductor heterojunction for use in a qubit register of a topological quantum computer includes measuring a radio-frequency (RF) junction admittance of the semiconductor-superconductor heterojunction to obtain mapping data; finding by analysis of the mapping data one or more regions of a parameter space consistent with an unbroken topological phase of the semiconductor-superconductor heterojunction; measuring a sub-RF conductance including a non-local conductance of the semiconductor-superconductor heterojunction in each of the one or more regions of the parameter space, to obtain refinement data; and finding by analysis of the refinement data a boundary of the unbroken topological phase in the parameter space and a topological gap of the semiconductor-superconductor heterojunction for at least one of the one or more regions of the parameter space.
    Type: Application
    Filed: May 28, 2020
    Publication date: September 9, 2021
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Dmitry PIKULIN, Mason L THOMAS, Chetan Vasudeo NAYAK, Roman Mykolayovych LUTCHYN, Georg Wolfgang WINKLER, Sebastian HEEDT, Gijsbertus DE LANGE, Bernard VAN HECK, Esteban Adrian MARTINEZ, Lucas CASPARIS, Torsten KARZIG
  • Patent number: 10692010
    Abstract: The disclosure relates to a quantum device and method of fabricating the same. The device comprises one or more semiconductor-superconductor nanowires, each comprising a length of semiconductor material and a coating of superconductor material coated on the semiconductor material. The nanowires may be formed over a substrate. In a first aspect at least some of the nanowires are full-shell nanowires with superconductor material being coated around a full perimeter of the semiconductor material along some or all of the length of the wire, wherein the device is operable to induce at least one Majorana zero mode, MZM, in one or more active ones of the full-shell nanowires. In a second aspect at least some of the nanowires are arranged vertically relative to the plane of the substrate in the finished device.
    Type: Grant
    Filed: September 3, 2018
    Date of Patent: June 23, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Michael Hartley Freedman, Bernard van Heck, Georg Wolfgang Winkler, Torsten Karzig, Roman Lutchyn, Peter Krogstrup Jeppesen, Chetan Nayak, Charles Masamed Marcus, Saulius Vaitiekenas
  • Patent number: 10665701
    Abstract: The disclosure relates to a quantum device and method of fabricating the same. The device comprises one or more semiconductor-superconductor nanowires, each comprising a length of semiconductor material and a coating of superconductor material coated on the semiconductor material. The nanowires may be formed over a substrate. In a first aspect at least some of the nanowires are full-shell nanowires with superconductor material being coated around a full perimeter of the semiconductor material along some or all of the length of the wire, wherein the device is operable to induce at least one Majorana zero mode, MZM, in one or more active ones of the full-shell nanowires. In a second aspect at least some of the nanowires are arranged vertically relative to the plane of the substrate in the finished device.
    Type: Grant
    Filed: September 3, 2018
    Date of Patent: May 26, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Michael Hartley Freedman, Bernard van Heck, Georg Wolfgang Winkler, Torsten Karzig, Roman Lutchyn, Peter Krogstrup Jeppesen, Chetan Nayak, Charles Masamed Marcus, Saulius Vaitiek─Śnas
  • Publication number: 20200027971
    Abstract: The disclosure relates to a quantum device and method of fabricating the same. The device comprises one or more semiconductor-superconductor nanowires, each comprising a length of semiconductor material and a coating of superconductor material coated on the semiconductor material. The nanowires may be formed over a substrate. In a first aspect at least some of the nanowires are full-shell nanowires with superconductor material being coated around a full perimeter of the semiconductor material along some or all of the length of the wire, wherein the device is operable to induce at least one Majorana zero mode, MZM, in one or more active ones of the full-shell nanowires. In a second aspect at least some of the nanowires are arranged vertically relative to the plane of the substrate in the finished device.
    Type: Application
    Filed: September 3, 2018
    Publication date: January 23, 2020
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Michael Hartley Freedman, Bernard van Heck, Georg Wolfgang Winkler, Torsten Karzig, Roman Lutchyn, Peter Krogstrup Jeppesen, Chetan Nayak, Charles Masamed Marcus, Saulius Vaitiekenas
  • Publication number: 20200027030
    Abstract: The disclosure relates to a quantum device and method of fabricating the same. The device comprises one or more semiconductor-superconductor nanowires, each comprising a length of semiconductor material and a coating of superconductor material coated on the semiconductor material. The nanowires may be formed over a substrate. In a first aspect at least some of the nanowires are full-shell nanowires with superconductor material being coated around a full perimeter of the semiconductor material along some or all of the length of the wire, wherein the device is operable to induce at least one Majorana zero mode, MZM, in one or more active ones of the full-shell nanowires. In a second aspect at least some of the nanowires are arranged vertically relative to the plane of the substrate in the finished device.
    Type: Application
    Filed: September 3, 2018
    Publication date: January 23, 2020
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Michael Hartley Freedman, Bernard van Heck, Georg Wolfgang Winkler, Torsten Karzig, Roman Lutchyn, Peter Krogstrup Jeppesen, Chetan Nayak, Charles Masamed Marcus, Saulius Vaitiekenas