Abstract: A Delta-Sigma .DELTA..SIGMA. modulator for one-bit analog to digital conversion of a signal, such as a telephone voice channel switch to digital form is disclosed. The circuit incorporates integration operative as low-pass filtering. The voice signal is sampled at a rate high compared to the highest voice channel frequency component. Sampled instantaneous signal values are integrated, re-sampled and again integrated to reduce encoding noise. Finally, a bi-level sense identifying circuit links the second integrator output to a D type flip-flop providing the one-bit encoded output.The sampling and integrator control is effected by switching in a capacitor charge shifting arrangement under clock control and feedback is applied as a capacitor switching program modifications.

Abstract: There is disclosed a decimator structure which incorporates the cascade of an FIR filter with a low pass recursive filter. The input to the decimator is obtained from a high rate analog to digital converter. The output from the decimator is a low rate digital signal having an increased word length. The decimator serves to reduce the word rate and increase the word length of the output digital signal of the analog to digital converter. In this manner, the low rate digital signal at the output of the decimator can be easily accommodated by the telephone system. The decimator described does not require conventional hardware multipliers and hence, affords efficient and economical circuit components which can be implemented by conventional integrated circuit techniques. A register further reduces the pulse rate for transmission.

Abstract: There is disclosed a digital gain control particularly adapted for use with digital signals propagating in a telephone line circuit. The gain control is positioned in the circuit to respond to a digital signal manifesting a plurality of words, each having a given number of bits N and indicative of a weighted value of an analog signal. The digital signal is multiplied by a word coefficient having a number of bits M indicative of a gain factor to be imparted to the digital signal. A product signal is provided containing M+N bits. The least significant bits are removed to provide an output signal of N bits possessing the desired gain. The discarded bits are employed via a feedback loop and are added to the next word product, which is then used to provide a next output signal. The feedback loop assures that each output signal is a close approximation to the input signal as gain controlled by the desired gain factor.

Abstract: A digital to analog converter is employed in the digital line circuit of a telephone system and operates to convert a digital signal indicative of an analog speech signal back into a replica of the analog signal. The converter operates with an interpolated input digital signal to detect by means of a sign bit, the characteristic of an input digital word as being indicative of a positive or negative level. An error correcting signal is provided by the converter which is added to the next digital word to provide a compensated word having a sign bit determined by the remainder and the sign bit of the previous digital word. This word is then processed in sequence to produce an output pulse stream from the sign detector indicative of successive positive or negative values as defined by the input digital words, each of which are modified according to the error correcting signal.

Abstract: This speech signal digital interpolator increases data (and date rate) by first using an interface unit for rate-changing and zero-stuffing a 32 Kiloword/sec (13 bits/word) signal to form a 1.024 Megaword/sec (13 bits/word) signal, which is then smoothed by a low-pass filter and approximated with 3-bit words. The interface circuit repeats each word a given number of times at the increased rate with each word separated by an all zero bit word having the same number of bits as the digital word to provide an output signal of a specified pattern for each word in the digital signal. A low pass recursive filter responds to the output signal from the interface means and is operative to provide a filtered output digital signal having smooth transitions between each output digital word with said filter output signal at said increased rate and with each output filtered digital word being of a lesser number of bits than the bits in said original signal.

Abstract: The present invention discloses an adaptive digital echo cancellation circuit including a finite impulse response digital filter, wherein the digital filter coefficients are adapted by continuous updating to compensate for telephone subscriber line echo conditions to enable the digital filter to continuously simulate the instantaneous subscriber line echo. The continuous coefficient update is provided by a correlator which includes provision for introducing non-linearities into the PCM transmitted and received signals, in parallel with the speech path, to derive a simplified digital representation of the PCM speech, thereby reducing the signal processing hardware required by the correlator to derive the updated filter coefficients.