Patents by Inventor Bharat PENMECHA

Bharat PENMECHA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240128205
    Abstract: Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.
    Type: Application
    Filed: December 27, 2023
    Publication date: April 18, 2024
    Inventors: Debendra MALLIK, Ravindranath MAHAJAN, Robert SANKMAN, Shawna LIFF, Srinivas PIETAMBARAM, Bharat PENMECHA
  • Publication number: 20240038687
    Abstract: Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.
    Type: Application
    Filed: October 13, 2023
    Publication date: February 1, 2024
    Inventors: Debendra MALLIK, Ravindranath MAHAJAN, Robert SANKMAN, Shawna LIFF, Srinivas PIETAMBARAM, Bharat PENMECHA
  • Patent number: 11824018
    Abstract: Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.
    Type: Grant
    Filed: December 27, 2022
    Date of Patent: November 21, 2023
    Inventors: Debendra Mallik, Ravindranath Mahajan, Robert Sankman, Shawna Liff, Srinivas Pietambaram, Bharat Penmecha
  • Patent number: 11735533
    Abstract: Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: August 22, 2023
    Assignee: Intel Corporation
    Inventors: Debendra Mallik, Ravindranath Mahajan, Robert Sankman, Shawna Liff, Srinivas Pietambaram, Bharat Penmecha
  • Publication number: 20230134049
    Abstract: Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.
    Type: Application
    Filed: December 27, 2022
    Publication date: May 4, 2023
    Inventors: Debendra MALLIK, Ravindranath MAHAJAN, Robert SANKMAN, Shawna LIFF, Srinivas PIETAMBARAM, Bharat PENMECHA
  • Publication number: 20230089093
    Abstract: Embodiments disclosed herein include electronic packages and methods of assembling such electronic packages. In an embodiment, an electronic package comprises a core, where the core comprises glass. In an embodiment, a plug is formed through the core, where the plug comprises a magnetic material. In an embodiment, an inductor is around the plug. In an embodiment, first layers are over the core, wherein where the first layers comprise a dielectric material; and second layers are under the core, where the second layers comprise the dielectric material.
    Type: Application
    Filed: September 23, 2021
    Publication date: March 23, 2023
    Inventors: Srinivas V. PIETAMBARAM, Tarek A. IBRAHIM, Krishna BHARATH, Bharat PENMECHA, Anderw COLLINS, Kaladhar RADHAKRISHNAN, Sriram SRINIVASAN
  • Publication number: 20200395313
    Abstract: Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.
    Type: Application
    Filed: June 11, 2019
    Publication date: December 17, 2020
    Inventors: Debendra MALLIK, Ravindranath MAHAJAN, Robert SANKMAN, Shawna LIFF, Srinivas PIETAMBARAM, Bharat PENMECHA
  • Publication number: 20190393112
    Abstract: Embodiments include an encapsulation material, one or more semiconductor packages, and methods of the semiconductor packages. A semiconductor package including dies disposed on a package substrate. The semiconductor package also includes at least one of an underfill layer, a mold layer, and a dielectric layer on or in the package substrate. The semiconductor package further includes an encapsulation material having a fluorescent chemical compound and an epoxy. The encapsulation material may be incorporated into at least one of the underfill layer, the mold layer, and/or the dielectric layer on or in the package substrate. The fluorescent chemical compound of the encapsulation material may include at least one of a poly(vinylcarbazole) (PVCz), a 1,4-Bis(5-phenyl-2-oxazolyl) benzene (POPOP), and/or a plurality of conjugated, aromatic molecules and polymers. The encapsulation material may include at least one of a hardener, a filler, an additive, and/or a polymer.
    Type: Application
    Filed: June 25, 2018
    Publication date: December 26, 2019
    Inventors: Elizabeth NOFEN, Bharat PENMECHA, Arjun KRISHNAN, Malavarayan SANKARASUBRAMANIAN