Abstract: A system includes a controller configured to receive a signal indicating whether a droop event has occurred. The system also includes a plurality of delay elements where each delay element of the plurality of delay elements responsive to a signal from the controller receives an input signal and outputs an output signal that is a delayed version of the input signal. At least one delay element of the plurality of delay elements receives a clocking signal as its input signal. The system also includes a selector configured to select rising edges and falling edges of output signals from the plurality of delay elements to form a modified clocking signal. The modified clocking signal is a modified version of the clocking signal.

Abstract: A system includes a controller configured to receive a signal indicating whether a droop event has occurred. The system also includes a plurality of delay elements where each delay element of the plurality of delay elements responsive to a signal from the controller receives an input signal and outputs an output signal that is a delayed version of the input signal. At least one delay element of the plurality of delay elements receives a clocking signal as its input signal. The system also includes a selector configured to select rising edges and falling edges of output signals from the plurality of delay elements to form a modified clocking signal. The modified clocking signal is a modified version of the clocking signal.

Abstract: A system includes a controller configured to receive a signal indicating whether a droop event has occurred. The system also includes a plurality of delay elements where each delay element of the plurality of delay elements responsive to a signal from the controller receives an input signal and outputs an output signal that is a delayed version of the input signal. At least one delay element of the plurality of delay elements receives a clocking signal as its input signal. The system also includes a selector configured to select rising edges and falling edges of output signals from the plurality of delay elements to form a modified clocking signal. The modified clocking signal is a modified version of the clocking signal.

Abstract: A system includes a plurality of delay elements configured to receive an input clock signal. The system further includes an edge transition detector coupled to the plurality of delay elements. The plurality of delay elements is configured to detect the input clock signal transitioning from one value to another value. The system also includes a circuitry configured to determine a number of delay elements of the plurality of delay elements that the input clock signal propagates through prior to the input clock signal transitioning. The system also includes a logic or controller configured to determine whether a droop event has occurred based on the number of delay elements.

Abstract: A system includes a controller configured to receive a signal indicating whether a droop event has occurred. The system also includes a plurality of delay elements where each delay element of the plurality of delay elements responsive to a signal from the controller receives an input signal and outputs an output signal that is a delayed version of the input signal. At least one delay element of the plurality of delay elements receives a clocking signal as its input signal. The system also includes a selector configured to select rising edges and falling edges of output signals from the plurality of delay elements to form a modified clocking signal. The modified clocking signal is a modified version of the clocking signal.

Abstract: A system includes a plurality of delay elements configured to receive an input clock signal. The system further includes an edge transition detector coupled to the plurality of delay elements. The plurality of delay elements is configured to detect the input clock signal transitioning from one value to another value. The system also includes a circuitry configured to determine a number of delay elements of the plurality of delay elements that the input clock signal propagates through prior to the input clock signal transitioning. The system also includes a logic or controller configured to determine whether a droop event has occurred based on the number of delay elements.

Abstract: A sense amplifier circuit includes: a data line; a sense amplifier output node; a keeper circuit; a logic gate; a noise threshold circuit; and an inverter. The keeper circuit includes a first transistor and a second transistor connected in series and coupled between a first power node and the data line. A gate node of the first transistor is coupled to the sense amplifier output node. The logic gate has an input connected to the bit line and an output connected to the sense amplifier output node. The noise threshold circuit includes: a third transistor and a fourth transistor connected in series between a second power node and the sense amplifier output node; and an inverter connected between a gate node of the third transistor and the sense amplifier output node.

Abstract: An integrated circuit includes a global power supply node. A first power domain has a first power management circuit, which includes a local power supply node. A first power control circuit is capable of receiving an input signal. A second power control circuit has a higher current capacity than the first power control circuit. The first power control circuit and the second power control circuit are coupled to the local power supply node and the global power supply node. The input signal is configured to initiate a power sequence, e.g., a power up process or a power down process, in the first power control circuit. A first control signal generated by the first power control circuit is configured to initiate a power sequence in the second power control circuit.

Abstract: A sense amplifier circuit includes: a data line; a sense amplifier output node; a keeper circuit; a logic gate; a noise threshold circuit; and an inverter. The keeper circuit includes a first transistor and a second transistor connected in series and coupled between a first power node and the data line. A gate node of the first transistor is coupled to the sense amplifier output node. The logic gate has an input connected to the bit line and an output connected to the sense amplifier output node. The noise threshold circuit includes: a third transistor and a fourth transistor connected in series between a second power node and the sense amplifier output node; and an inverter connected between a gate node of the third transistor and the sense amplifier output node.

Abstract: A sense amplifier circuit includes a power node having a power node voltage at a power voltage level, a bit line having a bit line voltage, a sense amplifier output, an NMOS transistor and a PMOS transistor coupled in series between the power node and the bit line, and a logic gate configured to generate a sense amplifier output voltage at the sense amplifier output based on the bit line voltage. The NMOS transistor is configured to operate in a sub-threshold region to maintain the bit line voltage at a first level and operate in a region above the sub-threshold region to maintain the bit line voltage at a second level, and the first level is between the second level and the power voltage level.

Abstract: A sense amplifier circuit includes a power node having a power node voltage at a power voltage level, a bit line having a bit line voltage, a sense amplifier output, an NMOS transistor and a PMOS transistor coupled in series between the power node and the bit line, and a logic gate configured to generate a sense amplifier output voltage at the sense amplifier output based on the bit line voltage. The NMOS transistor is configured to operate in a sub-threshold region to maintain the bit line voltage at a first level and operate in a region above the sub-threshold region to maintain the bit line voltage at a second level, and the first level is between the second level and the power voltage level.

Abstract: A sense amplifier includes a first transistor having a first gate, a second transistor having a second gate in series with the first transistor, a third transistor having a third gate, and a fourth transistor having a fourth gate in series with the third transistor. A first input node is coupled to the third gate and the fourth gate, a second input node is coupled to the first gate and the second gate, and a first compensation transistor is in series with the first and second transistors or the third and fourth transistors, the first compensation transistor having a first compensation bulk. The first compensation bulk receives a first compensation voltage to modify the first compensation threshold, the first compensation voltage having a value calculated to compensate for an offset associated with the first and second input nodes.

Abstract: A method of maintaining a voltage level of a bit line of a sense amplifier circuit includes providing a power supply voltage at a power supply node, receiving the power supply voltage from the power supply node with an NMOS transistor, and maintaining a voltage level of the bit line by supplying sufficient current with the NMOS transistor to compensate a leakage current of the bit line. The method includes receiving the voltage level of the bit line with a noise threshold control circuit, inverting the voltage level with the noise threshold control circuit, and driving a sense amplifier output with the noise threshold control circuit.

Abstract: Systems and methods are provided for reducing surge current in power gated designs. In one aspect, a storage capacitor supplies a portion of the current used to power up a circuit. The storage capacitor may be charged from a power supply or other source. When the circuit is to be powered up, the circuit is connected to the power supply and the storage capacitor. As a result, current is supplied to the circuit from the power supply and the storage capacitor to power up the circuit. Because a portion of the current used to power up the circuit is supplied from the storage capacitor, the amount of current needed from the power supply to power up the circuit can be reduced, thereby reducing current surge through the power supply. The storage capacitor may be shared by multiple circuits.

Abstract: A sense amplifier includes a first transistor having a first gate, a second transistor having a second gate in series with the first transistor, a third transistor having a third gate, and a fourth transistor having a fourth gate in series with the third transistor. A first input node is coupled to the third gate and the fourth gate, a second input node is coupled to the first gate and the second gate, and a first compensation transistor is in series with the first and second transistors or the third and fourth transistors, the first compensation transistor having a first compensation bulk. The first compensation bulk receives a first compensation voltage to modify the first compensation threshold, the first compensation voltage having a value calculated to compensate for an offset associated with the first and second input nodes.

Abstract: A method of maintaining a voltage level of a bit line of a sense amplifier circuit includes providing a power supply voltage at a power supply node, receiving the power supply voltage from the power supply node with an NMOS transistor, and maintaining a voltage level of the bit line by supplying sufficient current with the NMOS transistor to compensate a leakage current of the bit line. The method includes receiving the voltage level of the bit line with a noise threshold control circuit, inverting the voltage level with the noise threshold control circuit, and driving a sense amplifier output with the noise threshold control circuit.

Abstract: A method of re-offsetting a plurality of amplifier is provided. The method includes testing the plurality of amplifiers based on a re-offset value at bulks of compensation transistors of the plurality of amplifiers; identifying a first group of first amplifiers of the plurality of amplifiers favoring reading a first logic level and/or a second group of second amplifiers of the plurality of amplifiers favoring reading a second logic level different from the first logic level, based on results of the testing step; changing the re-offset value to a new re-offset value; re-offsetting the first group of first amplifiers and/or the second group of second amplifiers based on the new re-offset value; and re-testing the first group of first amplifiers and the second group of second amplifiers.

Abstract: Systems and methods are provided for reducing surge current in power gated designs. In one aspect, a storage capacitor supplies a portion of the current used to power up a circuit. The storage capacitor may be charged from a power supply or other source. When the circuit is to be powered up, the circuit is connected to the power supply and the storage capacitor. As a result, current is supplied to the circuit from the power supply and the storage capacitor to power up the circuit. Because a portion of the current used to power up the circuit is supplied from the storage capacitor, the amount of current needed from the power supply to power up the circuit can be reduced, thereby reducing current surge through the power supply. The storage capacitor may be shared by multiple circuits.

Abstract: In at least one embodiment, a sense amplifier circuit includes a bit line, a sense amplifier output, a keeper circuit, and a noise threshold control circuit. The keeper circuit is coupled to the bit line and includes an NMOS transistor coupled between a power node and the bit line. The keeper circuit is sized to supply sufficient current to compensate a leakage current of the bit line and configured to maintain a voltage level of the bit line. The noise threshold control circuit is connected to the sense amplifier output and the bit line. The noise threshold control circuit comprises an inverter.

Abstract: In at least one embodiment, a sense amplifier circuit includes a bit line, a sense amplifier output, a keeper circuit, and a noise threshold control circuit. The keeper circuit is coupled to the bit line and includes an NMOS transistor coupled between a power node and the bit line. The keeper circuit is sized to supply sufficient current to compensate a leakage current of the bit line and configured to maintain a voltage level of the bit line. The noise threshold control circuit is connected to the sense amplifier output and the bit line. The noise threshold control circuit comprises an inverter.