Abstract: A piezoelectric device comprises: a substrate (12) and a lead magnesium niobate-lead titanate (PMNPT) piezoelectric film on the substrate (12). The PMNPT film comprises: a thermal oxide layer (20) on the substrate (12); a first electrode above on the thermal oxide layer (20); a seed layer (26) above the first electrode; a lead magnesium niobate-lead titanate (PMNPT) piezoelectric layer (16) on the seed layer (26), and a second electrode on the PMNPT piezoelectric layer (16). The PMNPT film comprises a piezoelectric coefficient (d33) of greater than or equal to 200 pm/V.

Abstract: Examples disclosed herein relate to piezoelectric devices and methods of patterning piezoelectric layers for piezoelectric device fabrication. In certain embodiments, a piezoelectric layer disposed over a bottom electrode layer on a substrate is selectively etched via a laser etching process to expose portions of the bottom electrode layer. The laser etching process of the piezoelectric layer facilitates improvement of throughput and reduces hazardous byproduct production during fabrication of piezoelectric devices.

Abstract: Disclosed are methods and apparatus for depositing uniform layers on a substrate (201) for piezoelectric applications. An ultra-thin seed layer (308) having a uniform thickness from center to edge thereof is deposited on a substrate (201). A template layer (310) closely matching the crystal structure of a subsequently formed piezoelectric material layer (312) is deposited on a substrate (201). The uniform thickness and orientation of the seed layer (308) and the template layer (310), in turn, facilitate the growth of piezoelectric materials with improved crystallinity and piezoelectric properties.

Abstract: Embodiments described herein relate to a method of fabricating a perovskite film device. The method includes heating and degassing a substrate within a processing system; depositing a first perovskite film layer over a surface of the substrate using multi-cathode sputtering deposition within a processing chamber; depositing a second perovskite film layer over the first perovskite film layer using multi-cathode sputtering deposition within a processing chamber; and annealing the substrate with the first perovskite film layer and second perovskite film layer disposed thereon. The first perovskite film layer includes a first perovskite material. The second perovskite film layer includes a second perovskite material.

Abstract: A physical vapor deposition system includes a deposition chamber, a support to hold a substrate in the deposition chamber, a target in the chamber, a power supply configured to apply power to the target to generate a plasma in the chamber to sputter material from the target onto the substrate to form a piezoelectric layer on the substrate, and a controller configured to cause the power supply to alternate between deposition phases in which the power supply applies power to the target and cooling phases in which power supply does not apply power to the target. Each deposition phase lasts at least 30 seconds and each cooling phase lasts at least 30 seconds.

Abstract: A method of fabricating a piezoelectric layer includes depositing a piezoelectric material onto a substrate in a first crystallographic phase by physical vapor deposition while the substrate remains at a temperature below 400° C., and thermally annealing the substrate at a temperature above 500° C. to convert the piezoelectric material to a second crystallographic phase. The physical vapor deposition includes sputtering from a target in a plasma deposition chamber.

Abstract: Doped-aluminum nitride (doped-AlN) films and methods of manufacturing doped-AlN films are disclosed. Some methods comprise forming alternating pinning layers and doped-AlN layers including a dopant selected from the group consisting of Sc, Y, Hf, Mg, Zr and Cr, wherein the pinning layers pin the doped-AlN layers to a c-axis orientation. Some methods include forming a conducting layer including a material selected from the group consisting of Mo, Pt, Ta, Ru, LaNiO3 and SrRuO3. Some methods include forming a thermal oxide layer having silicon oxide on a silicon substrate. Piezoelectric devices comprising the doped-AlN film are also disclosed.

Abstract: Methods and apparatus for processing a substrate using improved shield configurations are provided herein. For example, a process kit for use in a physical vapor deposition chamber includes a shield comprising an inner wall with an innermost diameter configured to surround a target when disposed in the physical vapor deposition chamber, wherein a ratio of a surface area of the shield to a planar area of the inner diameter is about 3 to about 10.

Abstract: A piezoelectric device includes a substrate, a thermal oxide layer on the substrate, a metal or metal oxide adhesion layer on the thermal oxide layer, a lower electrode on the metal oxide adhesion layer, a seed layer on the lower electrode, a lead magnesium niobate-lead titanate (PMNPT) piezoelectric layer on the seed layer, and an upper electrode on the PMNPT piezoelectric layer.

Abstract: A method of fabricating a piezoelectric layer includes depositing a piezoelectric material onto a substrate in a first crystallographic phase by physical vapor deposition while the substrate remains at a temperature below 400° C., and thermally annealing the substrate at a temperature above 500° C. to convert the piezoelectric material to a second crystallographic phase. The physical vapor deposition includes sputtering from a target in a plasma deposition chamber.

Abstract: In one embodiment a superconductor tape includes a substrate comprising a plurality of layers, an oriented superconductor layer disposed on the substrate, and an alloy coating disposed upon the superconductor layer, the alloy coating comprising one or more metallic layers in which at least one metallic layer comprises a metal alloy.

Abstract: A superconductor tape includes a plurality of conductive strips having respective long directions parallel to a long tape direction of the superconductor tape, where each of the plurality of conductive strips separated from one another by a inter-strip region. The superconductor tape further includes a superconductor layer disposed adjacent the plurality of conductive strips, having a length along the long tape direction, where the superconductor layer comprises a plurality of superconductor strips disposed under the respective plurality of conductive strips, and a non-superconductor strip disposed adjacent the inter-strip region.

Abstract: A superconductor tape includes a plurality of conductive strips having respective long directions parallel to a long tape direction of the superconductor tape, where each of the plurality of conductive strips separated from one another by a inter-strip region. The superconductor tape further includes a superconductor layer disposed adjacent the plurality of conductive strips, having a length along the long tape direction, where the superconductor layer comprises a plurality of superconductor strips disposed under the respective plurality of conductive strips, and a non-superconductor strip disposed adjacent the inter-strip region.

Abstract: In one embodiment a superconductor tape includes a substrate comprising a plurality of layers, an oriented superconductor layer disposed on the substrate, and an alloy coating disposed upon the superconductor layer, the alloy coating comprising one or more metallic layers in which at least one metallic layer comprises a metal alloy.

Abstract: Systems, methods, and devices that facilitate stacking dies in a multi-die stack using die support mechanisms (DSMs) are presented. DSMs are employed to place a smaller die and attached wires underneath a larger die. DSMs can be placed on each side of the smaller die where the larger die overhangs when placed above the smaller die. The DSMs can be optimally sized to provide support to the larger die to reduce overhang and sagging, while providing a buffer region to protect the smaller die and associated wires. DSMs are employed to facilitate stacking dies that are the same or similar in size by placing a DSM between the dies. The DSM can be optimally sized to provide a buffer region to protect the wires bonded to the top side of the lower die from the upper die, while minimizing overhang to provide support to the upper die.