Patents by Inventor Bhyrav M. Mutnury

Bhyrav M. Mutnury has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11985760
    Abstract: A printed circuit board (PCB), including: a ground reference layer; a pre-impregnated (pre-preg) layer having a surface; a first transmission line positioned on the surface; a second transmission line positioned on the surface spaced-apart from the first transmission line a first distance; and a solder mask layer positioned on the surface of the pre-preg layer and surrounding the first transmission line and the second transmission line, the solder mask layer having a thickness and a dielectric constant, wherein the thickness of the solder mask layer and a value of the dielectric constant of the solder mask layer cause convergence of electric fields associated with the first transmission line to be within a second distance from the first transmission line.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: May 14, 2024
    Assignee: Dell Products L.P.
    Inventors: Douglas S. Winterberg, Wan-Ju Kuo, Bhyrav M. Mutnury
  • Patent number: 11977436
    Abstract: Systems and methods are provided for management of PCIe bandwidth within an IHS (Information Handling System). A PCIe connection is detected between a first of the processors of the IHS and a solid-state drive accessed via a DPU (Data Processing Unit). In a processor core of the DPU (e.g., ARM core) buffers are initialized for tracking specific types of errors in the PCIe connection. Upon detecting an error in the PCIe connection, the error is added to one of the designated buffers based on a type of the detected error. If adding of the error in the PCIe connection to the buffer results in a size limit of the buffer being reached, and if the size of the buffer cannot be reduced through retransmission of the errors in the buffer, a transmission speed of the PCIe connection is downgraded, thus extending operations at higher transmission speeds.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: May 7, 2024
    Assignee: Dell Products, L.P.
    Inventors: Bhavesh Govindbhai Patel, Arun Chada, Bhyrav M. Mutnury
  • Publication number: 20240028406
    Abstract: Systems and methods provide circuit optimizations using a mech architecture of an IHS (Information Handling System). A control block operated by a CPU of the IHS determines availability of mesh resources, including resources of a removeable processor of the IHS. The control block reserves available resources of the removeable processor for use in a circuit optimization. The control block assigns a portion of the circuit optimization to the removeable processor. A mesh client operated by the replaceable processor calculates a result by processing the assigned portion of the circuit optimization. The mesh client also tracks the use of resource of the removeable processor during the calculation of the assigned portion of the circuit optimization. The results of the calculation and a log specifying the tracked use of the resources of the removeable processor are transmitted to the control block to determine updates to the mesh resources that are reserved.
    Type: Application
    Filed: July 22, 2022
    Publication date: January 25, 2024
    Applicant: Dell Products, L.P.
    Inventors: Bhavesh Govindbhai Patel, Arun Chada, Bhyrav M. Mutnury
  • Publication number: 20240028448
    Abstract: Systems and methods provide management of PCIe bandwidth within an IHS (Information Handling System) through predictive evaluation of signaling degradation in PCIe lanes of the IHS. Upon initialization of the IHS, a DPU (Data Processing Unit) generates baseline signal integrity measurements for PCIe links supported by a PCIe interface of the DPU. A signaling analytic model operated by the DPU is calibrated using the baseline signal integrity measurements. A signal degradation prediction is generated by the signaling analytics model. When the signal degradation prediction is confirmed versus observed degradation in the PCIe interface, use of the signaling analytics model is activated. The activated signaling analytics module is then utilized to predict a signaling degradation in a connection supported by the PCIe interface of the DPU. In response to the prediction by the activated signaling analytics model, a corrective operation is initiated in order to prevent the predicted signaling degradation.
    Type: Application
    Filed: July 20, 2022
    Publication date: January 25, 2024
    Applicant: Dell Products, L.P.
    Inventors: Arun Chada, Bhyrav M. Mutnury, Bhavesh Govindbhai Patel
  • Publication number: 20240028437
    Abstract: Systems and methods are provided for management of PCIe bandwidth within an IHS (Information Handling System). A PCIe connection is detected between a first of the processors of the IHS and a solid-state drive accessed via a DPU (Data Processing Unit). In a processor core of the DPU (e.g., ARM core) buffers are initialized for tracking specific types of errors in the PCIe connection. Upon detecting an error in the PCIe connection, the error is added to one of the designated buffers based on a type of the detected error. If adding of the error in the PCIe connection to the buffer results in a size limit of the buffer being reached, and if the size of the buffer cannot be reduced through retransmission of the errors in the buffer, a transmission speed of the PCIe connection is downgraded, thus extending operations at higher transmission speeds.
    Type: Application
    Filed: July 20, 2022
    Publication date: January 25, 2024
    Applicant: Dell Products, L.P.
    Inventors: Bhavesh Govindbhai Patel, Arun Chada, Bhyrav M. Mutnury
  • Patent number: 11835576
    Abstract: Compensating for signal loss, including determining a first expected loss at a first frequency and a second expected loss at a second frequency at a receiver associated with a first lane of a PCB; calculating an expected rate of change of signal loss between the first and the second frequencies based on the first and the second expected losses; calculating a first measured loss of a first signal transmitted at the first frequency and a second measured loss of a second signal transmitted at the second frequency from a transmitter to the receiver along the first lane of the PCB; calculating a measured rate of change of signal loss between the first and second frequencies based on the first and the second measured losses; comparing the measured rate of change with the expected rate of change; compensating a gain of a signal transmitted from the transmitter to the receiver.
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: December 5, 2023
    Assignee: Dell Products L.P.
    Inventors: Bhyrav M. Mutnury, Sandor Farkas
  • Patent number: 11837828
    Abstract: A memory module socket, including a first member extending between a first end and a second end of the socket, the second end of the socket opposite to the first end of the socket, the first member positioned along a first side of the socket, the first member including: a plurality of first contact pins, each of the first contact pins including a first contact point and a second contact point; a plurality of first resistive coatings connecting two or more of the first contact pins to define first groupings of contact pins; a plurality of first ribs separating each of the first groupings of first contact pins; wherein when the first contact pins are in a first position, the second contact points of the first contact pins are in contact with respective first resistive coatings to complete a termination to ground.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: December 5, 2023
    Assignee: Dell Products L.P.
    Inventors: Bhyrav M. Mutnury, Mark A. Smith, Sandor Farkas
  • Publication number: 20230344174
    Abstract: A computing cable that connects computing elements, including: a trace including a first trace segment and a second trace segment, the trace having a first impedance; and an attenuator connecting the first trace segment to the second trace segment, the attenuator including: a resistor having a resistance, and a conductor having a second impedance, wherein the combination of the resistance and the second impedance is based on the first impedance.
    Type: Application
    Filed: April 26, 2022
    Publication date: October 26, 2023
    Inventors: Bhyrav M. MUTNURY, Sandor FARKAS
  • Patent number: 11800646
    Abstract: Methods and systems are provided for designing an optimized stack up of layers of a PCB (Printed Circuit Board). A set of constraints is determined for the PCB stack up, where the constraints limit a total number of layers, a number of signal layers, and a thickness of the PCB stack up. Each of the constraints on the PCB stack up is encoded as an equality or an inequality. The set of equalities and inequalities is solved using integer programming techniques to identify an optimal solution to the set of constraints on the PCB stack up, where the optimal solution specifies an arrangement of signaling layers for the PCB. An estimate is generated for impedances and losses for the optimal PCB stack up. The constraints on a PCB stack up are modified when the estimated impedances and losses for the optimal PCB stack up are above a target threshold.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: October 24, 2023
    Assignee: Dell Products, L.P.
    Inventors: Bhavesh Govindbhai Patel, Arun Chada, Bhyrav M. Mutnury
  • Publication number: 20230337354
    Abstract: A printed circuit board (PCB), including: a ground reference layer; a pre-impregnated (pre-preg) layer having a surface; a first transmission line positioned on the surface; a second transmission line positioned on the surface spaced-apart from the first transmission line a first distance; and a solder mask layer positioned on the surface of the pre-preg layer and surrounding the first transmission line and the second transmission line, the solder mask layer having a thickness and a dielectric constant, wherein the thickness of the solder mask layer and a value of the dielectric constant of the solder mask layer cause convergence of electric fields associated with the first transmission line to be within a second distance from the first transmission line.
    Type: Application
    Filed: April 19, 2022
    Publication date: October 19, 2023
    Inventors: Douglas S. Winterberg, Wan-Ju Kuo, Bhyrav M. Mutnury
  • Publication number: 20230335953
    Abstract: A connection assembly including a receptacle connector having a first and a second end, including: a shell, including a first outer surface and a second outer surface; a shield surrounding the shell, the shield including: a first portion including a first cam flange, the first portion rotatable about a first spring hinge; a second portion including a second cam flange, the second portion rotatable about a second spring hinge; a mating connector removable coupleable to the receptacle connector, including: an adjustment member, wherein, when a positioning of the adjustment member is adjusted to decrease a distance between the adjustment member and the second end of the receptacle connector, the adjustment member adjusts a distance between the first cam flange and the second cam flange to rotate the first portion of the shield about the first spring hinge and rotate the second portion of the shield about the second spring hinge.
    Type: Application
    Filed: April 19, 2022
    Publication date: October 19, 2023
    Inventors: Bhyrav M. Mutnury, Mark A. Smith, Sandor Farkas
  • Publication number: 20230319978
    Abstract: An information handling system includes a printed circuit board, a surface mount connector including first and second surface mount connector portions, first and second different pairs, and a ground plane. The first and second surface mount connector portions are mounted on the printed circuit board. The first differential pair is located on the first surface mount connector portion, and the second differential pair is located on the second surface mount connector portion. The ground plane is located in between the first and second surface mount connector portions within the printed circuit board. The first ground via is in physical communication with the ground plane and a first ground pad on a surface of the printed circuit board. The second ground via is in physical communication with the ground plane and a second ground pad on the surface of the printed circuit board.
    Type: Application
    Filed: April 5, 2022
    Publication date: October 5, 2023
    Inventors: William Andrew Smith, Mallikarjun Vasa, Bhyrav M. Mutnury
  • Patent number: 11774474
    Abstract: Embodiments described herein relate to a method for modifying transmission line characteristics. The method may include: making a first determination of a null frequency of an input signal to a transmission line; performing an analysis to make a second determination of a wavelength of the input signal using, at least in part, the null frequency; making a third determination, based on the analysis, of a half wavelength of the input signal; calculating, based on the half wavelength, a total stub length; and adding a trace to a stub associated with a via, wherein the stub and the trace are a length that is at least a portion of the half wavelength of the input signal.
    Type: Grant
    Filed: April 5, 2022
    Date of Patent: October 3, 2023
    Assignee: DELL PRODUCTS L.P.
    Inventors: Sandor T. Farkas, Bhyrav M. Mutnury
  • Publication number: 20230221367
    Abstract: Compensating for signal loss, including determining a first expected loss at a first frequency and a second expected loss at a second frequency at a receiver associated with a first lane of a PCB; calculating an expected rate of change of signal loss between the first and the second frequencies based on the first and the second expected losses; calculating a first measured loss of a first signal transmitted at the first frequency and a second measured loss of a second signal transmitted at the second frequency from a transmitter to the receiver along the first lane of the PCB; calculating a measured rate of change of signal loss between the first and second frequencies based on the first and the second measured losses; comparing the measured rate of change with the expected rate of change; compensating a gain of a signal transmitted from the transmitter to the receiver.
    Type: Application
    Filed: January 13, 2022
    Publication date: July 13, 2023
    Inventors: Bhyrav M. Mutnury, Sandor Farkas
  • Publication number: 20230171898
    Abstract: Back drilling vias of a PCB, including: identifying a particular diameter of a particular via of multiple vias of the PCB; back drilling of the particular via with a first drill bit having a first diameter, the first diameter a first percentage greater than the particular diameter of the particular via; determining whether the first diameter of the first drill bit is a threshold percentage greater than the particular diameter of the particular via; determining that the first diameter of the first drill bit is less than the threshold percentage greater than the particular diameter of the particular via, and in response: back drilling of the particular via with a second drill bit having a second diameter, the second diameter a second percentage greater than the particular diameter of the particular via, the second diameter greater than the first diameter.
    Type: Application
    Filed: December 1, 2021
    Publication date: June 1, 2023
    Inventors: Steven Richard Ethridge, Ching-Huei Chen, Bhyrav M. Mutnury
  • Patent number: 11646515
    Abstract: A connection assembly, including: a first connector having a first end and a second end, and a first surface extending between the first end and the second end, the first connector including press fit pins extending away from the first surface, each of the press fit pins including: a rod portion; a connecting portion having a first shape; a second connector having a first end and a second end, including: a dielectric carrier having a first surface extending between the first end and the second end of the second connector, receptacles positioned within the first surface of the dielectric carrier, each of the receptacles including: a cylindrical region, a tapered region having a second shape that corresponds to the first shape of the connection portion, wherein, when the first connector is coupled to the second connector, the press fit pins are positioned within respective receptacles of the receptacles.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: May 9, 2023
    Assignee: Dell Products L.P.
    Inventors: Bhyrav M. Mutnury, Mark A. Smith, Sanjiv C. Sinha, Sandor Farkas
  • Publication number: 20230130196
    Abstract: A memory module socket, including a first member extending between a first end and a second end of the socket, the second end of the socket opposite to the first end of the socket, the first member positioned along a first side of the socket, the first member including: a plurality of first contact pins, each of the first contact pins including a first contact point and a second contact point; a plurality of first resistive coatings connecting two or more of the first contact pins to define first groupings of contact pins; a plurality of first ribs separating each of the first groupings of first contact pins; wherein when the first contact pins are in a first position, the second contact points of the first contact pins are in contact with respective first resistive coatings to complete a termination to ground.
    Type: Application
    Filed: October 21, 2021
    Publication date: April 27, 2023
    Inventors: Bhyrav M. Mutnury, Mark A. Smith, Sandor Farkas
  • Publication number: 20230128773
    Abstract: A connection assembly, including: a first connector having a first end and a second end, and a first surface extending between the first end and the second end, the first connector including press fit pins extending away from the first surface, each of the press fit pins including: a rod portion; a connecting portion having a first shape; a second connector having a first end and a second end, including: a dielectric carrier having a first surface extending between the first end and the second end of the second connector, receptacles positioned within the first surface of the dielectric carrier, each of the receptacles including: a cylindrical region, a tapered region having a second shape that corresponds to the first shape of the connection portion, wherein, when the first connector is coupled to the second connector, the press fit pins are positioned within respective receptacles of the receptacles.
    Type: Application
    Filed: October 21, 2021
    Publication date: April 27, 2023
    Inventors: Bhyrav M. Mutnury, Mark A. Smith, Sanjiv C. Sinha, Sandor Farkas
  • Patent number: 11604745
    Abstract: An information handling system may include a processor, a device communicatively coupled to a processor via a communications link including a cable assembly, and a management controller communicatively coupled to the processor and communicatively coupled to the device and the cable assembly via a sideband interface, and configured to: retrieve, via the sideband interface, self-describing signal integrity critical parameters from non-transitory computer-readable media integral to the device; retrieve, via the sideband interface, self-describing signal integrity critical parameters from non-transitory computer-readable media integral to the cable assembly; combine the self-describing signal integrity critical parameters from non-transitory computer-readable media integral to the device and the self-describing signal integrity critical parameters from non-transitory computer-readable media integral to the cable assembly into aggregate signal integrity critical parameters; and perform an action relevant to the co
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: March 14, 2023
    Assignee: Dell Products L.P.
    Inventors: Timothy M. Lambert, Bhyrav M. Mutnury, Sandor Farkas
  • Patent number: 11593530
    Abstract: An information handling system includes an intrusion detection circuit having two inductors and an amplifier circuit. The amplifier circuit is configured to identify an increase in inductive coupling between the inductors in response to a change in position of a cover.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: February 28, 2023
    Assignee: Dell Products L.P.
    Inventors: Sandor Farkas, Bhyrav M. Mutnury