Patents by Inventor Bich-Yen Nguyen

Bich-Yen Nguyen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100289113
    Abstract: The present invention relates to a method for manufacturing a hybrid semiconductor substrate comprising the steps of (a) providing a hybrid semiconductor substrate comprising a semiconductor-on-insulator (SeOI) region, that comprises an insulating layer over a base substrate and a SeOI layer over the insulating layer, and a bulk semiconductor region, wherein the SeOI region and the bulk semiconductor region share the same base substrate; (b) providing a mask layer over the SeOI region; and (c) forming a first impurity level by doping the SeOI region and the bulk semiconductor region simultaneously such that the first impurity level in the SeOI region is contained within the mask. Thereby avoiding higher number of process steps involved in the manufacturing process of hybrid semiconductor substrate.
    Type: Application
    Filed: March 18, 2010
    Publication date: November 18, 2010
    Applicant: S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES
    Inventors: Konstantin Bourdelle, Bich-Yen Nguyen, Mariam Sadaka
  • Patent number: 7821067
    Abstract: An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the electronic device may be formed by forming an oxidation mask over the first semiconductor portion. A second semiconductor layer can be formed over the second semiconductor portion of the first semiconductor layer and have a different composition compared to the first semiconductor layer. An oxidation can be performed, and a concentration of a semiconductor element (e.g., germanium) within the second portion of the first semiconductor layer can be increased. In another embodiment, a selective condensation may be performed, and a field isolation region can be formed between the first and second portions of the first semiconductor layer.
    Type: Grant
    Filed: August 10, 2007
    Date of Patent: October 26, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Voon-Yew Thean, Brian J. Goolsby, Linda B. McCormick, Bich-Yen Nguyen, Colita M. Parker, Mariam G. Sadaka, Victor H. Vartanian, Ted R. White, Melissa O. Zavala
  • Patent number: 7811382
    Abstract: A wafer having a silicon layer that is strained is used to form transistors. The silicon layer is formed by first forming a silicon germanium (SiGe) layer of at least 30 percent germanium that has relaxed strain on a donor wafer. A thin silicon layer is epitaxially grown to have tensile strain on the relaxed SiGe layer. The amount tensile strain is related to the germanium concentration. A high temperature oxide (HTO) layer is formed on the thin silicon layer by reacting dichlorosilane and nitrous oxide at a temperature of preferably between 800 and 850 degrees Celsius. A handle wafer is provided with a supporting substrate and an oxide layer that is then bonded to the HTO layer. The HTO layer, being high density, is able to hold the tensile strain of the thin silicon layer. The relaxed SiGe layer is cleaved then etched away to expose the thin silicon layer.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: October 12, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mariam G. Sadaka, Alexander L. Barr, Bich-Yen Nguyen, Voon-Yew Thean, Ted R. White
  • Patent number: 7803670
    Abstract: A semiconductor process and apparatus provide a dual or hybrid substrate by forming a second semiconductor layer (214) that is isolated from, and crystallographically rotated with respect to, an underlying first semiconductor layer (212) by a buried insulator layer (213); forming an STI region (218) in the second semiconductor layer (214) and buried insulator layer (213); exposing the first semiconductor layer (212) in a first area (219) of a STI region (218); epitaxially growing a first epitaxial semiconductor layer (220) from the exposed first semiconductor layer (212); and selectively etching the first epitaxial semiconductor layer (220) and the second semiconductor layer (214) to form CMOS FinFET channel regions (e.g., 223) and planar channel regions (e.g., 224) from the first epitaxial semiconductor layer (220) and the second semiconductor layer (214).
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: September 28, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ted R. White, Leo Mathew, Bich-Yen Nguyen, Zhonghai Shi, Voon-Yew Thean, Mariam G. Sadaka
  • Patent number: 7800141
    Abstract: An electronic device can include a semiconductor fin overlying an insulating layer. The electronic device can also include a semiconductor layer overlying the semiconductor fin. The semiconductor layer can have a first portion and a second portion that are spaced-apart from each other. In one aspect, the electronic device can include a conductive member that lies between and spaced-apart from the first and second portions of the semiconductor layer. The electronic device can also include a metal-semiconductor layer overlying the semiconductor layer. In another aspect, the semiconductor layer can abut the semiconductor fin and include a dopant. In a further aspect, a process of forming the electronic device can include reacting a metal-containing layer and a semiconductor layer to form a metal-semiconductor layer. In another aspect, a process can include forming a semiconductor layer, including a dopant, abutting a wall surface of a semiconductor fin.
    Type: Grant
    Filed: July 16, 2008
    Date of Patent: September 21, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Da Zhang, Bich-Yen Nguyen
  • Patent number: 7781277
    Abstract: An integrated circuit includes NMOS and PMOS transistors. The NMOS has a strained channel having first and second stress values along first and second axes respectively. The PMOS has a strained channel having third and fourth stress values along the first and second axes. The first value stress differs from the third value and the second value differs from the fourth value. The NMOS and PMOS have a common length (L) and effective width (W), but differ in length of diffusion (SA) and/or width of source/drain (WS). The NMOS WS may exceed the PMOS WS. The NMOS may include multiple dielectric structures in the active layer underlying the gate. The SA of the PMOS may be less than the SA of the NMOS. The integrated circuit may include a tensile stressor of silicon nitride over the NMOS and a compressive stressor of silicon nitride over the PMOS.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: August 24, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Bich-Yen Nguyen, Voon-Yew Thean
  • Patent number: 7781840
    Abstract: Two different transistors types are made on different crystal orientations in which both are formed on SOI. A substrate has an underlying semiconductor layer of one of the crystal orientations and an overlying layer of the other crystal orientation. The underlying layer has a portion exposed on which is epitaxially grown an oxygen-doped semiconductor layer that maintains the crystalline structure of the underlying semiconductor layer. A semiconductor layer is then epitaxially grown on the oxygen-doped semiconductor layer. An oxidation step at elevated temperatures causes the oxide-doped region to separate into oxide and semiconductor regions. The oxide region is then used as an insulation layer in an SOI structure and the overlying semiconductor layer that is left is of the same crystal orientation as the underlying semiconductor layer. Transistors of the different types are formed on the different resulting crystal orientations.
    Type: Grant
    Filed: May 1, 2007
    Date of Patent: August 24, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ted R. White, Alexander L. Barr, Bich-Yen Nguyen, Marius K. Orlowski, Mariam G. Sadaka, Voon-Yew Thean
  • Patent number: 7781839
    Abstract: A semiconductor device (10) comprising a substrate (12) and an oxide layer (14) formed over the substrate is provided. The semiconductor device further includes a first semiconductor layer (16) having a first lattice constant formed directly over the oxide layer. The semiconductor device further includes a second semiconductor layer (26) having a second lattice constant formed directly over the first semiconductor layer, wherein the second lattice constant is different from the first lattice constant.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: August 24, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Voon-Yew Thean, Bich-Yen Nguyen
  • Patent number: 7737496
    Abstract: An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the electronic device may be formed by forming an oxidation mask over the first semiconductor portion. A second semiconductor layer can be formed over the second semiconductor portion of the first semiconductor layer and have a different composition compared to the first semiconductor layer. An oxidation can be performed, and a concentration of a semiconductor element (e.g., germanium) within the second portion of the first semiconductor layer can be increased. In another embodiment, a selective condensation may be performed, and a field isolation region can be formed between the first and second portions of the first semiconductor layer.
    Type: Grant
    Filed: August 10, 2007
    Date of Patent: June 15, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Voon-Yew Thean, Brian J. Goolsby, Linda B. McCormick, Bich-Yen Nguyen, Colita M. Parker, Mariam G. Sadaka, Victor H. Vartanian, Ted R. White, Melissa O. Zavala
  • Patent number: 7700420
    Abstract: A substrate includes a first region and a second region. The first region comprises a III-nitride layer, and the second region comprises a first semiconductor layer. A first transistor (such as an n-type transistor) is formed in and on the III-nitride layer, and a second transistor (such as a p-type transistor) is formed in and on the first semiconductor layer. The III-nitride layer may be indium nitride. In the first region, the substrate may include a second semiconductor layer, a graded transition layer over the second semiconductor layer, and a buffer layer over the transition layer, where the III-nitride layer is over the buffer layer. In the second region, the substrate may include the second semiconductor layer and an insulating layer over the second semiconductor layer, where the first semiconductor layer is over the insulating layer.
    Type: Grant
    Filed: April 12, 2006
    Date of Patent: April 20, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Voon-Yew Thean, Bich-Yen Nguyen, Mariam G. Sadaka, Victor H. Vartanian, Ted R. White
  • Publication number: 20100059817
    Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type and a first doping concentration. A first semiconductor region, used as drain, of the first conductivity type has a lower doping concentration than the semiconductor layer and is over the semiconductor layer. A gate dielectric is over the first semiconductor region. A gate electrode over the gate dielectric has a metal-containing center portion and first and second silicon portions on opposite sides of the center portion. A second semiconductor region, used as a channel, of the second conductivity type has a first portion under the first silicon portion and the gate dielectric. A third semiconductor region, used as a source, of the first conductivity type is laterally adjacent to the first portion of the second semiconductor region. The metal-containing center portion, replacing silicon, increases the source to drain breakdown voltage.
    Type: Application
    Filed: September 5, 2008
    Publication date: March 11, 2010
    Inventors: DANIEL PHAM, Bich-Yen Nguyen
  • Patent number: 7645651
    Abstract: A method of forming a metal oxide semiconductor (MOS) device comprises defining an active area in an unstrained semiconductor layer structure, depositing a hard mask overlying the active area and a region outside of the active area, patterning the hard mask to expose the active area, selectively growing a strained semiconductor layer overlying the exposed active area, and forming a remainder of the MOS device. The active area includes a first doped region of first conductivity type and a second doped region of second conductivity type. The strained semiconductor layer provides a biaxially strained channel for the MOS device.
    Type: Grant
    Filed: December 6, 2007
    Date of Patent: January 12, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xiaoqiu Huang, Veeraraghavan Dhandapani, Bich-Yen Nguyen, Amanda M. Kroll, Daniel T. Pham
  • Publication number: 20090321829
    Abstract: In preferred embodiments, the invention provides substrates that include a support, a first insulating layer arranged on the support, a non-mono-crystalline semi-conducting layer arranged on the first insulating layer, a second insulating layer arranged on the non-mono-crystalline semi-conducting layer; and top layer disposed on the second insulating layer. Additionally, a first gate electrode can be formed on the top layer and a second gate electrode can be formed in the non-mono-crystalline semi-conducting layer. The invention also provides methods for manufacture of such substrates.
    Type: Application
    Filed: May 21, 2009
    Publication date: December 31, 2009
    Inventors: Bich-Yen Nguyen, Carlos Mazure
  • Publication number: 20090321873
    Abstract: In one embodiment, the invention provides substrates that are structured so that devices fabricated in a top layer thereof have properties similar to the same devices fabricated in a standard high resistivity substrate. Substrates of the invention include a support having a standard resistivity, a semiconductor layer arranged on the support substrate having a high-resistivity, preferably greater than about 1000 Ohms-cm, an insulating layer arranged on the high-resistivity layer, and a top layer arranged on the insulating layer. The invention also provides methods for manufacturing such substrates.
    Type: Application
    Filed: May 21, 2009
    Publication date: December 31, 2009
    Inventors: Bich-Yen Nguyen, Carlos Mazure
  • Publication number: 20090321872
    Abstract: In one embodiment, the invention provides engineered substrates having a support with surface pits, an intermediate layer of amorphous material arranged on the surface of the support so as to at least partially fill the surface pits, and a top layer arranged on the intermediate layer. The invention also provides methods for manufacturing the engineered substrates which deposit an intermediate layer on a pitted surface of a support so as to at least partially fill the surface pits, then anneal the intermediate layer, then assemble a donor substrate with the annealed intermediate layer to form an intermediate structure, and finally reduce the thickness of the donor substrate portion of the intermediate structure in order to form the engineered substrate.
    Type: Application
    Filed: May 20, 2009
    Publication date: December 31, 2009
    Inventors: Bich-Yen Nguyen, Carlos Mazure
  • Patent number: 7615806
    Abstract: Forming a semiconductor structure includes providing a substrate having a strained semiconductor layer overlying an insulating layer, providing a first device region for forming a first plurality of devices having a first conductivity type, providing a second device region for forming a second plurality of devices having a second conductivity type, and thickening the strained semiconductor layer in the second device region so that the strained semiconductor layer in the second device region has less strain that the strained semiconductor layer in the first device region. Alternatively, forming a semiconductor structure includes providing a first region having a first conductivity type, forming an insulating layer overlying at least an active area of the first region, anisotropically etching the insulating layer, and after anisotropically etching the insulating layer, deposing a gate electrode material overlying at least a portion of the insulating layer.
    Type: Grant
    Filed: October 31, 2005
    Date of Patent: November 10, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Voon-Yew Thean, Jian Chen, Bich-Yen Nguyen, Mariam G. Sadaka, Da Zhang
  • Patent number: 7585735
    Abstract: A method of forming a semiconductor device is provided in which a substrate (102) is provided which has a gate dielectric layer (106) disposed thereon, and a gate electrode (116) having first and second sidewalls is formed over the gate dielectric layer. First (146) and second (150) extension spacer structures are formed adjacent the first and second sidewalls, respectively.
    Type: Grant
    Filed: February 1, 2005
    Date of Patent: September 8, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Leo Mathew, Yang Du, Bich-Yen Nguyen, Voon-Yew Thean
  • Publication number: 20090218625
    Abstract: A semiconductor process and apparatus includes forming first and second metal gate electrodes (151, 161) over a hybrid substrate (17) by forming the first gate electrode (151) over a first high-k gate dielectric (121) and forming the second gate electrode (161) over at least a second high-k gate dielectric (122) different from the first gate dielectric (121). By forming the first gate electrode (151) over a first SOI substrate (90) formed by depositing (100) silicon and forming the second gate electrode (161) over an epitaxially grown (110) SiGe substrate (70), a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes (161) having improved hole mobility.
    Type: Application
    Filed: April 9, 2009
    Publication date: September 3, 2009
    Inventors: Olubunmi O. Adetutu, Mariam G. Sadaka, Ted R. White, Bich-Yen Nguyen
  • Patent number: 7575975
    Abstract: Forming a semiconductor structure includes providing a substrate having a strained semiconductor layer overlying an insulating layer, providing a first device region for forming a first plurality of devices having a first conductivity type, providing a second device region for forming a second plurality of devices having a second conductivity type, and thickening the strained semiconductor layer in the second device region so that the strained semiconductor layer in the second device region has less strain that the strained semiconductor layer in the first device region. Alternatively, forming a semiconductor structure includes providing a first region having a first conductivity type, forming an insulating layer overlying at least an active area of the first region, anisotropically etching the insulating layer, and after anisotropically etching the insulating layer, deposing a gate electrode material overlying at least a portion of the insulating layer.
    Type: Grant
    Filed: October 31, 2005
    Date of Patent: August 18, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Voon-Yew Thean, Jian Chen, Bich-Yen Nguyen, Mariam G. Sadaka, Da Zhang
  • Patent number: 7575968
    Abstract: A semiconductor process and apparatus provide a high performance CMOS devices (108, 109) with hybrid or dual substrates by etching a deposited oxide layer (62) using inverse slope isolation techniques to form tapered isolation regions (76) and expose underlying semiconductor layers (41, 42) in a bulk wafer structure prior to epitaxially growing the first and second substrates (84, 82) having different surface orientations that may be planarized with a single CMP process. By forming first gate electrodes (104) over a first substrate (84) that is formed by epitaxially growing (100) silicon and forming second gate electrodes (103) over a second substrate (82) that is formed by epitaxially growing (110) silicon, a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes having improved hole mobility.
    Type: Grant
    Filed: April 30, 2007
    Date of Patent: August 18, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mariam G. Sadaka, Debby Eades, Joe Mogab, Bich-Yen Nguyen, Melissa O. Zavala, Gregory S. Spencer