Patents by Inventor Bill Liu

Bill Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210358993
    Abstract: A pixel cell includes a plurality of subpixels to generate image charge in response to incident light. The subpixels include an inner subpixel laterally surrounded by outer subpixels. A first plurality of transfer gates disposed proximate to the inner subpixel and a first grouping of outer subpixels. A first floating diffusion is coupled to receive the image charge from the first grouping of outer subpixels through a first plurality of transfer gates. A second plurality of transfer gates disposed proximate to the inner subpixel and the second grouping of outer subpixels. A second floating diffusion disposed in the semiconductor material and coupled to receive the image charge from each one of the second grouping of outer subpixels through the second plurality of transfer gates. The image charge in the inner subpixel is received by the first, second, or both floating diffusions through respective transfer gates.
    Type: Application
    Filed: May 18, 2020
    Publication date: November 18, 2021
    Inventors: Duli Mao, Bill Phan, Keiji Mabuchi, Seong Yeol Mun, Yuanliang Liu, Vincent Venezia
  • Patent number: 10541544
    Abstract: Techniques and systems are described that enable multiple current source prioritization with overvoltage protection.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: January 21, 2020
    Assignee: MIASOLÉ HI-TECH CORP.
    Inventors: Hyung Paek, Jia-Jay Bill Liu, Thomas Aquinas Heckel, Nicholai Busch, Uriel Rosas Rivera, James Teixeira, Nicolas Guerrero, Jason Stephen Corneille, Richard Weinberg
  • Publication number: 20190267819
    Abstract: Techniques and systems are described that enable multiple current source prioritization with overvoltage protection.
    Type: Application
    Filed: May 14, 2019
    Publication date: August 29, 2019
    Inventors: Hyung Paek, Jia-Jay Bill Liu, Thomas Aquinas Heckel, Nicholai Busch, Uriel Rosas Rivera, James Teixeira, Nicolas Guerrero, Jason Stephen Corneille, Richard Weinberg
  • Patent number: 8821218
    Abstract: A method for manufacturing a magnetic disk is provided that includes the steps: forming a layer of a lubricant material on a surface of a magnetic storage medium, the layer of lubricant material also being located on an interior and/or exterior edge of the medium; and removing at least some of the lubricant material from the edge 160 of the medium.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: September 2, 2014
    Assignee: Seagate Technology LLC
    Inventors: Thuan Luu, Walter Crofton, Bill Liu, David Spaulding, Kwang Kon Kim
  • Patent number: 8467240
    Abstract: Nonvolatile memory element circuitry is provided that is based on metal-oxide-semiconductor transistor structures. A nonvolatile memory element may be based on a metal-oxide-semiconductor transistor structure that has a gate, a drain, a source, and a body. During programming operations, control circuitry floats the body while applying a positive voltage to the drain and a negative voltage to the source. This causes the drain and source, which serve as the collector and emitter in a parasitic bipolar transistor, to break down. The drain-to-source (collector-to-emitter) breakdown causes sufficient current to flow through the source to alter the source electrode and thereby increase the resistance of the source significantly. During sensing operations, control circuitry may apply a voltage across the drain and source while grounding the body to determine whether the memory element has been programmed.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: June 18, 2013
    Assignee: Altera Corporation
    Inventors: Albert Ratnakumar, Shuang Xie, Cheng-Hsiung Huang, Yow-Juang Bill Liu
  • Patent number: 8438351
    Abstract: A method and computer-readable memory device that enable processing of a first memory image comprising a plurality of compressed sub-blocks and uncompressed sub-blocks to produce a second memory image comprising contents of the first memory image arranged as a plurality of memory blocks. The memory blocks of the second memory image may be independently decompressible, to enable more efficient updating of an electronic device.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: May 7, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Samson Chen, Marko Slyz, LaShawn McGhee, Giovanni Motta, Brian O'Neill, Bill Liu, Li Wen, Ben-Tong Sun
  • Patent number: 8232602
    Abstract: The present invention includes a circuit structure for ESD protection and methods of making the circuit structure. The circuit structure can be used in an ESD protection circuitry to protect certain devices in an integrated circuit, and can be fabricated without extra processing steps in addition to the processing steps for fabricating the ESD protected devices in the integrated circuit.
    Type: Grant
    Filed: February 23, 2007
    Date of Patent: July 31, 2012
    Assignee: Altera Corporation
    Inventors: Yowjuang (Bill) Liu, Cheng Huang
  • Patent number: 8159044
    Abstract: An integrated circuit is provided with a spiral inductor and a transition zone surrounding the spiral inductor. The transition zone may have a geometry that is substantially eight-sided or octagonal. Metal layers in the transition zone may have metal fill that is substantially octagonal and arranged in rows and columns. If desired, square or rectangular metal fill be tiled with the substantially octagonal metal fill. Metal layers may also contain halved or quartered octagonal metal fill. Substrate in the transition zone may have octagonal substrate regions separated by shallow trench isolation regions. A polysilicon layer above the substrate may have square regions of polysilicon fill directly above the shallow trench regions in the substrate. Such arrangements may provide more uniform densities in transition zones with certain geometries.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: April 17, 2012
    Assignee: Altera Corporation
    Inventors: Shuxian Chen, Fangyun Richter, Bradley Jensen, Yowjuang (Bill) Liu
  • Patent number: 8116130
    Abstract: Nonvolatile memory element circuitry is provided that is based on metal-oxide-semiconductor transistor structures. A nonvolatile memory element may be based on a metal-oxide-semiconductor transistor structure that has a gate, a drain, a source, and a body. During programming operations, control circuitry floats the body while applying a positive voltage to the drain and a negative voltage to the source. This causes the drain and source, which serve as the collector and emitter in a parasitic bipolar transistor, to break down. The drain-to-source (collector-to-emitter) breakdown causes sufficient current to flow through the source to alter the source electrode and thereby increase the resistance of the source significantly. During sensing operations, control circuitry may apply a voltage across the drain and source while grounding the body to determine whether the memory element has been programmed.
    Type: Grant
    Filed: September 1, 2009
    Date of Patent: February 14, 2012
    Assignee: Altera Corporation
    Inventors: Albert Ratnakumar, Shuang Xie, Cheng-Hsiung Huang, Yow-Juang Bill Liu
  • Patent number: 8089744
    Abstract: An integrated circuit (IC) includes a multiple-finger transistor structure. The multiple-finger transistor structure includes one transistor configured as a ballasted device. The multiple-finger transistor structure further includes a second transistor configured as a trigger device for the ballasted device.
    Type: Grant
    Filed: August 24, 2005
    Date of Patent: January 3, 2012
    Assignee: Altera Corporation
    Inventors: Irfan Rahim, Cheng Hsiung Huang, Yow-Juang Bill Liu, Jeffrey T. Watt, Hugh Sung-Ki O
  • Patent number: 7981753
    Abstract: A device for providing electrostatic discharge (ESD) protection is provided. The device includes a semiconductor substrate having a drain, a source, and a gate formed therein. The drain contains a region having a resistance that is higher than the resistance of the remainder of the drain and the source. The gate region is in contact with this higher resistance region and the source. In one embodiment, the higher resistance is lacking silicide in order to provide the higher resistance. A method of forming a device for providing ESD protection is included.
    Type: Grant
    Filed: January 6, 2010
    Date of Patent: July 19, 2011
    Assignee: Altera Corporation
    Inventors: Hugh Sungki O, Chih-Ching Shih, Cheng-Hsiung Huang, Yow-Juang Bill Liu
  • Publication number: 20110107046
    Abstract: A method and computer-readable memory device that enable processing of a first memory image comprising a plurality of compressed sub-blocks and uncompressed sub-blocks to produce a second memory image comprising contents of the first memory image arranged as a plurality of memory blocks. The memory blocks of the second memory image may be independently decompressible, to enable more efficient updating of an electronic device.
    Type: Application
    Filed: June 6, 2008
    Publication date: May 5, 2011
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Samson Chen, Marko Slyz, LaShawn McGhee, Giovanni Motta, Brian O'Neill, Bill Liu, Li Wen, Ben-Tong Sun
  • Patent number: D727945
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: April 28, 2015
    Assignee: Microsoft Corporation
    Inventors: Alan Andrew Urdan, Moneta K. Ho Kushner, Karen Scott, Mary-Lynne Williams, Orry Wijanarko Soegiono, Bill Liu
  • Patent number: D727946
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: April 28, 2015
    Assignee: Microsoft Corporation
    Inventors: Alan Andrew Urdan, Moneta K. Ho Kushner, Karen Scott, Mary-Lynne Williams, Orry Wijanarko Soegiono, Bill Liu
  • Patent number: D728605
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: May 5, 2015
    Assignee: Microsoft Corporation
    Inventors: Alan Andrew Urdan, Moneta K. Ho Kushner, Karen Scott, Mary-Lynne Williams, Orry Wijanarko Soegiono, Bill Liu
  • Patent number: D728606
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: May 5, 2015
    Assignee: Microsoft Corporation
    Inventors: Alan Andrew Urdan, Moneta K. Ho Kushner, Karen Scott, Mary-Lynne Williams, Orry Wijanarko Soegiono, Bill Liu
  • Patent number: D728608
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: May 5, 2015
    Assignee: Microsoft Corporation
    Inventors: Alan Andrew Urdan, Moneta K. Ho Kushner, Karen Scott, Mary-Lynne Williams, Orry Wijanarko Soegiono, Bill Liu
  • Patent number: D732561
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: June 23, 2015
    Assignee: Microsoft Corporation
    Inventors: Alan Andrew Urdan, Moneta K. Ho Kushner, Karen Scott, Mary-Lynne Williams, Orry Wijanarko Soegiono, Bill Liu
  • Patent number: D740301
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: October 6, 2015
    Assignee: Microsoft Corporation
    Inventors: Orry Wijanarko Soegiono, Bill Liu, Sean Wen, Mary-Lynne Williams, Ethan Nelson Ray, Moneta K. Ho Kushner
  • Patent number: D741898
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: October 27, 2015
    Assignee: Microsoft Corporation
    Inventors: Orry Wijanarko Soegiono, Bill Liu, Mary-Lynne Williams