Patents by Inventor Bill Nale

Bill Nale has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220229790
    Abstract: A memory module has data buffers coupled to a registered clock driver (RCD) via buffer communication (BCOM) bus. The memory module includes memory devices managed as a first pseudo channel and a second pseudo channel. The data buffers manage data transmission between the memory devices and a host based on commands received over the BCOM bus. The RCD can send a first BCOM command on the BCOM bus to the data buffer, the first BCOM command to specify a rank and a burst length for the first pseudo channel. The RCD can send a second BCOM command on the BCOM bus to the data buffer, the second BCOM command to specify a rank and a burst length for the second pseudo channel, and a timing offset relative to the first BCOM command.
    Type: Application
    Filed: March 31, 2022
    Publication date: July 21, 2022
    Inventor: Bill NALE
  • Publication number: 20220189532
    Abstract: A memory device with internal row hammer mitigation couples to a memory controller. The memory controller or host can assist with row hammer mitigation by sending additional refresh cycles or refresh commands. In response to an extra refresh command the memory device can perform refresh for row hammer mitigation instead of refresh for standard data integrity. The memory controller can keep track of the number of activate commands sent to the memory device, and in response to a threshold number of activate commands, the memory controller sends the additional refresh command. With the extra refresh command the memory device can refresh the potential victim rows of a potential aggressor row, instead of simply refreshing a row that has not been accessed for a period of time.
    Type: Application
    Filed: March 3, 2022
    Publication date: June 16, 2022
    Inventors: Bill NALE, Christopher E. COX
  • Publication number: 20220157374
    Abstract: A memory device is described. The memory device includes logic circuitry to perform calibrations of resistive network terminations and data drivers of the memory device while the memory device is within a self refresh mode.
    Type: Application
    Filed: February 7, 2022
    Publication date: May 19, 2022
    Inventors: Christopher E. COX, Bill NALE
  • Patent number: 11335395
    Abstract: A memory subsystem triggers entry and exit of a memory device from low power mode with a chip select (CS) signal line. For a system where the command bus has no clock enable (CKE) signal line, the system can trigger low power modes with CS instead of CKE. The low power mode can include a powerdown state. The low power mode can include a self-refresh state. The memory device includes an interface to the command bus, and receives a CS signal combined with command encoding on the command bus to trigger a low power mode state change. The memory device can be configured to monitor the CS signal and selected other command signals while in low power mode. The system can send an ODT trigger while the memory device is in low power mode, even without a dedicated ODT signal line.
    Type: Grant
    Filed: October 2, 2020
    Date of Patent: May 17, 2022
    Assignee: Intel Corporation
    Inventors: Christopher E. Cox, Kuljit S. Bains, Christopher P. Mozak, James A. McCall, Akshith Vasanth, Bill Nale
  • Publication number: 20220121398
    Abstract: A memory device can internally track row address activates for perfect row hammer tracking, incrementing an activate count for each row when an access command is received for a row. Instead of incrementing the count for each activate, the memory controller can indicate a number greater than one for the memory device to increment the count, and then indicate not to increment the count for subsequent accesses up to the number indicated. The memory controller can determine whether the row address of an activate command is one of N recent row addresses that received the access command. The memory controller can indicate an increment of zero if the row address is one of the N recent addresses, and indicate an increment of a number higher than one if the row address is not one of the N recent addresses.
    Type: Application
    Filed: December 23, 2021
    Publication date: April 21, 2022
    Inventors: Bill NALE, Kuljit S. BAINS
  • Patent number: 11282561
    Abstract: A memory device with internal row hammer mitigation couples to a memory controller. The memory controller or host can assist with row hammer mitigation by sending additional refresh cycles or refresh commands. In response to an extra refresh command the memory device can perform refresh for row hammer mitigation instead of refresh for standard data integrity. The memory controller can keep track of the number of activate commands sent to the memory device, and in response to a threshold number of activate commands, the memory controller sends the additional refresh command. With the extra refresh command the memory device can refresh the potential victim rows of a potential aggressor row, instead of simply refreshing a row that has not been accessed for a period of time.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: March 22, 2022
    Assignee: Intel Corporation
    Inventors: Bill Nale, Christopher E. Cox
  • Patent number: 11276453
    Abstract: A memory device is described. The memory device includes logic circuitry to perform calibrations of resistive network terminations and data drivers of the memory device while the memory device is within a self refresh mode.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: March 15, 2022
    Assignee: Intel Corporation
    Inventors: Christopher E. Cox, Bill Nale
  • Publication number: 20210365316
    Abstract: A memory chip is described. The memory chip includes storage cells along a row of the memory chip's storage cell array to store a count value of the row's activations and error correction code (ECC) information to protect the count value. The memory chip includes ECC read logic circuitry to correct an error in the count value. The memory chip includes a comparator to compare the count value against a threshold. The memory chip includes circuitry to increment the count value if the count value is deemed not to have reached the threshold and ECC write logic circuitry to determine new ECC information for the incremented count value, and write driver circuitry to write the incremented count value and the new ECC information into the storage cells. The memory chip includes circuitry to cause the row to be refreshed if the count value is deemed to have reached the threshold.
    Type: Application
    Filed: June 4, 2021
    Publication date: November 25, 2021
    Inventors: Bill NALE, Kuljit S. BAINS, Lawrence BLANKENBECKLER, Ronald ANDERSON, Jongwon LEE
  • Publication number: 20210336767
    Abstract: A memory subsystem includes link encryption for the system memory data bus. The memory controller can provide encryption for data at rest and link protection. The memory controller can optionally provide link encryption. Thus, the system can provide link protection for the data in transit. The memory module can include a link decryption engine that can decrypt link encryption if it is used, and performs a link integrity check with a link integrity tag associated with the link protection. The memory devices can then store the encrypted protected data and ECC data from the link decryption engine after link protection verification.
    Type: Application
    Filed: June 25, 2021
    Publication date: October 28, 2021
    Inventors: Raghunandan MAKARAM, Kirk S. YAP, Rajat AGARWAL, George VERGIS, Bill NALE, Jacob DOWECK
  • Publication number: 20210286561
    Abstract: For a memory device where a data fetch accesses N/2 data bits, and the memory device is to transfer N bits over a data burst of length M in response to a read command, the memory device accesses the same bank twice to access the N bits. Instead of accessing N/2 bits from two different banks, the memory device accesses a single bank twice. The memory device can control the timing of the data transfer to enable sending all N data bits to the memory controller for the read command. The memory device can send data as a first transfer of burst length M/2 of a first N/2 data bit portion and a second transfer of burst length M/2 of a second N/2 data bit portion.
    Type: Application
    Filed: June 2, 2021
    Publication date: September 16, 2021
    Inventors: Kuljit S. BAINS, Bill NALE
  • Publication number: 20210279128
    Abstract: A method is described. The method includes a buffer semiconductor chip receiving a plurality of data signals. The method includes the buffer chip calculating first CRC information from the plurality of data signals. The method includes the buffer chip transmitting the plurality of data signals in parallel with the first CRC information if a read burst transfer sequence is being performed, the buffer chip receiving second CRC information in parallel with the plurality of data signals and comparing the first CRC information with the second CRC information if a write burst transfer sequence is being performed.
    Type: Application
    Filed: May 21, 2021
    Publication date: September 9, 2021
    Inventors: James A. McCALL, Bill NALE, Zibing YANG, Yanjie ZHU
  • Publication number: 20210264999
    Abstract: A memory chip is described. The memory chip includes row hammer threat detection circuitry. The memory chip includes an output. The memory chip includes backpressure signal generation circuitry coupled between the row hammer detection circuitry and the output. The backpressure signal generation signal is to generate a backpressure signal to be sent from the output in response to detection by the row hammer threat detection circuitry of a row hammer threat.
    Type: Application
    Filed: May 8, 2021
    Publication date: August 26, 2021
    Inventors: Kuljit S. BAINS, Bill NALE, Jongwon LEE, Sreenivas MANDAVA
  • Publication number: 20210216238
    Abstract: An apparatus is described. The apparatus includes a register clock driver (RCD) semiconductor chip having first inputs to receive first command and address (CA) signals from a first sub-channel and first outputs to drive first and second instances of the CA information that are decoded from the first CA signals. The RCD semiconductor chip has second inputs to receive second command and address (CA) signals from a second sub-channel. The RCD semiconductor chip has a multiplexer having a first input channel to receive the first CA signals and a second input channel to receive the second CA signals. The RCD semiconductor chip has second outputs to drive third and fourth instances of the first CA information or first and second instances of the second CA information that are decoded from the second CA signals depending on which of the first and second input channels of the multiplexer is selected.
    Type: Application
    Filed: March 26, 2021
    Publication date: July 15, 2021
    Inventors: Bill NALE, George VERGIS
  • Publication number: 20210151095
    Abstract: A memory device with internal row hammer mitigation couples to a memory controller. The memory controller or host can assist with row hammer mitigation by sending additional refresh cycles or refresh commands. In response to an extra refresh command the memory device can perform refresh for row hammer mitigation instead of refresh for standard data integrity. The memory controller can keep track of the number of activate commands sent to the memory device, and in response to a threshold number of activate commands, the memory controller sends the additional refresh command. With the extra refresh command the memory device can refresh the potential victim rows of a potential aggressor row, instead of simply refreshing a row that has not been accessed for a period of time.
    Type: Application
    Filed: January 25, 2021
    Publication date: May 20, 2021
    Inventors: Bill NALE, Christopher E. COX
  • Publication number: 20210151083
    Abstract: Examples described herein relate to a device that includes: a first power rail to provide a signal from a power source to a reference supply voltage pin of a memory controller; a second power rail to provide a signal from the power source to an output buffer pin of the memory controller and to an output buffer pin of a central processing unit (CPU). In some examples, the second power rail is separate from the first power rail, during a high power state, the power source is to supply a same voltage to each of the reference supply voltage pin, the output buffer pin of the memory controller, and the output buffer pin of the CPU, and during a connected standby state, the power source is to reduce voltage provided to the output buffer pin of the memory controller and the output buffer pin of the CPU using the second power rail and maintain a voltage provided to the reference supply voltage pin.
    Type: Application
    Filed: December 23, 2020
    Publication date: May 20, 2021
    Inventors: Aiswarya M. PIOUS, Raji JAMES, Phani K. ALAPARTHI, George VERGIS, Bill NALE, Konika GANGULY
  • Publication number: 20210141692
    Abstract: A memory subsystem includes multiple memory resources connected in parallel, including a first memory resource and a second memory resource. The memory subsystem can split a portion of data into multiple sub-portions. Split into smaller portions, the system needs fewer ECC (error checking and correction) bits to provide the same level of ECC protection. The portion of data can include N ECC bits for error correction, and the sub-portions can each include a sub-portion of (N?M) ECC bits for error correction. The system can then use M bits of data for non-ECC purposes, such as metadata.
    Type: Application
    Filed: January 22, 2021
    Publication date: May 13, 2021
    Inventors: Rajat AGARWAL, Wei P. CHEN, Bill NALE, James A. McCALL
  • Patent number: 10997096
    Abstract: A memory subsystem enables per device addressability (PDA) to target configuration commands to one of multiple memory devices that share a select line or buffer devices that share an enable line. The system includes a host and multiple memory devices that can be coupled over a command bus and a data bus. The devices include a configuration or mode register to store a value to indicate whether PDA enumeration is enabled. When enabled, the host can provide an enumeration identifier (ID) command via the command bus with a signal via the data bus to assign an enumeration ID. After assignment of the enumeration ID, the host can send PDA commands via the command bus with the enumeration ID, without a signal on the data bus. Devices only process PDA commands that match their assigned enumeration ID, enabling the setting of device-specific configuration settings without needing to use the data bus on every PDA command.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: May 4, 2021
    Assignee: Intel Corporation
    Inventors: Tonia G. Morris, Bill Nale
  • Patent number: 10963404
    Abstract: A DIMM is described. The DIMM includes circuitry to simultaneously transfer data of different ranks of memory chips on the DIMM over a same data bus during a same burst write sequence.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: March 30, 2021
    Assignee: Intel Corporation
    Inventors: James A. McCall, Rajat Agarwal, George Vergis, Bill Nale
  • Patent number: 10950288
    Abstract: A memory device with internal row hammer mitigation couples to a memory controller. The memory controller or host can assist with row hammer mitigation by sending additional refresh cycles or refresh commands. In response to an extra refresh command the memory device can perform refresh for row hammer mitigation instead of refresh for standard data integrity. The memory controller can keep track of the number of activate commands sent to the memory device, and in response to a threshold number of activate commands, the memory controller sends the additional refresh command. With the extra refresh command the memory device can refresh the potential victim rows of a potential aggressor row, instead of simply refreshing a row that has not been accessed for a period of time.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: March 16, 2021
    Assignee: Intel Corporation
    Inventors: Bill Nale, Christopher E. Cox
  • Publication number: 20210020224
    Abstract: A memory subsystem triggers entry and exit of a memory device from low power mode with a chip select (CS) signal line. For a system where the command bus has no clock enable (CKE) signal line, the system can trigger low power modes with CS instead of CKE. The low power mode can include a powerdown state. The low power mode can include a self-refresh state. The memory device includes an interface to the command bus, and receives a CS signal combined with command encoding on the command bus to trigger a low power mode state change. The memory device can be configured to monitor the CS signal and selected other command signals while in low power mode. The system can send an ODT trigger while the memory device is in low power mode, even without a dedicated ODT signal line.
    Type: Application
    Filed: October 2, 2020
    Publication date: January 21, 2021
    Inventors: Christopher E. COX, Kuljit S. BAINS, Christopher P. MOZAK, James A. McCALL, Akshith VASANTH, Bill NALE