Abstract: An architecture for generating a hardware cursor in the context of a bit mapped video display system operable from a frame buffer with non-displayed but addressable memory space. A segment of the non-displayed memory is loaded with cursor outline and pattern information. The cursor data is accessed from the non-displayed segment of the memory during horizontal blank time preceding the raster scan of the video pattern data subject to cursor overlay. Thereby, the video pattern data in the frame buffer and cursor data are arranged by scan or row line. The column location of the cursor pattern is defined by the computer and stored in a position counter to be synchronously incremented by pixel during the scan of the frame buffer line. At the appropriate count the cursor data is logically combined with frame buffer pattern data to superimpose the cursor characteristics upon the video pattern data.