Patents by Inventor Bipin Rajendran
Bipin Rajendran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8933536Abstract: Memory cells having memory elements self-aligned with the emitters of bipolar junction transistor access devices are described herein, as well as methods for manufacturing such devices. A memory device as described herein comprises a plurality of memory cells. Memory cells in the plurality of memory cells include a bipolar junction transistor comprising an emitter comprising a pillar of doped polysilicon. The memory cells include an insulating element over the emitter and having an opening extending through the insulating layer, the opening centered over the emitter. The memory cells also include a memory element within the opening and electrically coupled to the emitter.Type: GrantFiled: January 22, 2009Date of Patent: January 13, 2015Assignees: Macronix International Co., Ltd., International Business Machines CorporationInventors: Hsiang-Lan Lung, Erh-Kun Lai, Chung H. Lam, Bipin Rajendran
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Patent number: 8898097Abstract: A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.Type: GrantFiled: August 16, 2012Date of Patent: November 25, 2014Assignee: International Business Machines CorporationInventors: Bernard V. Brezzo, Leland Chang, Steven K. Esser, Daniel J. Friedman, Yong Liu, Dharmendra S. Modha, Robert K. Montoye, Bipin Rajendran, Jae-sun Seo, Jose A. Tierno
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Patent number: 8856055Abstract: A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.Type: GrantFiled: April 8, 2011Date of Patent: October 7, 2014Assignee: International Business Machines CorporationInventors: Bernard V. Brezzo, Leland Chang, Steven K. Esser, Daniel J. Friedman, Yong Liu, Dharmendra S. Modha, Robert K. Montoye, Bipin Rajendran, Jae-sun Seo, Jose A. Tierno
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Patent number: 8832010Abstract: According to a technique, an electronic device is configured to correspond to characteristic features of a biological synapse. The electronic device includes multiple bipolar resistors arranged in parallel to form an electronic synapse, an axonal connection connected to one end of the electronic synapse and to a first electronic neuron, and a dendritic connection connected to another end of the electronic synapse and to a second electronic neuron. An increase and decrease of synaptic conduction in the electronic synapse is based on a probability of switching the plurality of bipolar resistors between a low resistance state and a high resistance state.Type: GrantFiled: January 4, 2012Date of Patent: September 9, 2014Assignee: International Business Machines CorporationInventors: Bipin Rajendran, Mark B. Ritter
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Patent number: 8832011Abstract: According to a technique, an electronic device is configured to correspond to characteristic features of a biological synapse. The electronic device includes multiple bipolar resistors arranged in parallel to form an electronic synapse, an axonal connection connected to one end of the electronic synapse and to a first electronic neuron, and a dendritic connection connected to another end of the electronic synapse and to a second electronic neuron. An increase and decrease of synaptic conduction in the electronic synapse is based on a probability of switching the plurality of bipolar resistors between a low resistance state and a high resistance state.Type: GrantFiled: September 12, 2012Date of Patent: September 9, 2014Assignee: International Business Machines CorporationInventors: Bipin Rajendran, Mark B. Ritter
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Patent number: 8824218Abstract: A compact, low-power, asynchronous, resistor-based memory read circuit includes a memory cell having a plurality of consecutive memory states, each of said states corresponding to a respective output voltage. A sense amplifier reads the state of the memory cell. The sense amplifier includes a voltage divider configured to receive the output voltage of the memory cell and to output a settled voltage an amplifier having a voltage threshold between the settled voltages associated with two of said consecutive memory states, configured to discriminate between said two consecutive memory states.Type: GrantFiled: July 19, 2012Date of Patent: September 2, 2014Assignee: International Business Machines CorporationInventors: Seongwon Kim, Yong Liu, Bipin Rajendran
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Publication number: 20140241048Abstract: A three dimensional (3D) stack of phase change memory (PCM) devices which includes PCM devices stacked in a 3D array, the PCM devices having memory regions; a memory management unit on at least one of the PCM devices; a stack controller in the memory management unit to monitor an ambient device temperature (Tambient) with respect to a neighborhood of memory regions in the PCM devices and to adjust a programming current with respect to at least one of the memory regions in the neighborhood of memory regions in accordance with the Tambient. Also disclosed is a method of programming a PCM device.Type: ApplicationFiled: February 25, 2013Publication date: August 28, 2014
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Patent number: 8772906Abstract: Memory cell structures for phase change memory. An example memory cell structure comprising includes a bottom electrode comprised of electrically conducting material, and phase change material disposed above the bottom electrode. A layer of thermally insulating material is disposed, at least partially, between the bottom electrode and the phase change material. The thermally insulating material is comprised of Tantalum Oxide. A top electrode is comprised of electrically conducting material.Type: GrantFiled: July 22, 2013Date of Patent: July 8, 2014Assignee: International Business Machines CorporationInventors: Matthew J. BrightSky, Roger W. Cheek, Chung H. Lam, Eric A. Joseph, Bipin Rajendran, Alejandro G. Schrott, Yu Zhu
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Publication number: 20140078837Abstract: A compact, low-power, asynchronous, resistor-based memory read circuit includes a memory cell having a plurality of consecutive memory states, each of said states corresponding to a respective output voltage. A sense amplifier reads the state of the memory cell. The sense amplifier includes a voltage divider configured to receive the output voltage of the memory cell and to output a settled voltage an amplifier having a voltage threshold between the settled voltages associated with two of said consecutive memory states, configured to discriminate between said two consecutive memory states.Type: ApplicationFiled: July 19, 2012Publication date: March 20, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: SEONGWON KIM, Yong Liu, Bipin Rajendran
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Publication number: 20140063925Abstract: Embodiments of the present invention provide a device comprising a plurality of phase change memory cells, a word line, and a plurality of bit lines. Each phase change memory cell is coupled to a corresponding transistor. Each transistor is coupled to the word line. Each bit line is coupled to a phase change memory cell of the device. The device further comprises a programming circuit configured to program at least one phase change memory cell to the SET state by selectively applying a two-stage waveform to the word line and the bit lines of the device. In a first stage, a first predetermined low voltage and a first predetermined high voltage are applied at the word line and the bit lines, respectively. In a second stage, a second predetermined high voltage and a predetermined voltage with decreasing amplitude are applied at the word line and the bit lines, respectively.Type: ApplicationFiled: March 29, 2012Publication date: March 6, 2014Applicant: International Business Machines CorporationInventors: Daniel J. Friedman, Seongwon Kim, Yong Liu, Bipin Rajendran
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Publication number: 20140065787Abstract: An integrated circuit includes a substrate including isolation regions, a first conductive line formed in the substrate between isolation regions, and a vertical diode formed in the substrate. The integrated circuit includes a contact coupled to the vertical diode and a memory element coupled to the contact. The first conductive line provides a portion of the vertical diode.Type: ApplicationFiled: November 7, 2013Publication date: March 6, 2014Applicants: International Business Machines Corporation, Qimonda AG, Macronix International Co., Ltd.Inventors: Thomas Happ, Hsiang-Lan Lung, Bipin Rajendran, Min Yang
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Patent number: 8648326Abstract: An example embodiment is a phase change memory cell that includes a bottom contact and an electrically insulating layer disposed over the bottom contact. The electrically insulating layer defines an elongated via. Furthermore, a bottom electrode is disposed at least partially in the via. The bottom electrode includes a sleeve of a first electrically conductive material surrounding a rod of a second electrically conductive material. The first electrically conductive material and the second electrically conductive material have different specific electrical resistances. The memory cell also includes a phase change layer electrically coupled to the first electrode.Type: GrantFiled: July 27, 2011Date of Patent: February 11, 2014Assignee: International Business Machines CorporationInventors: Matthew J. Breitwisch, Bipin Rajendran
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Patent number: 8637844Abstract: The present invention, in one embodiment, provides a method of producing a PN junction the method including at least the steps of providing a Si-containing substrate; forming an insulating layer on the Si-containing substrate; forming a via through the insulating layer to expose at least a portion of the Si-containing substrate; forming a seed layer of the exposed portion of the Si containing substrate; forming amorphous Si on at least the seed layer; converting at least a portion of the amorphous Si to provide crystalline Si; and forming a first dopant region abutting a second dopant region in the crystalline Si.Type: GrantFiled: April 29, 2011Date of Patent: January 28, 2014Assignees: International Business Machines Corporation, Macronix International Co., Ltd., Qimonda AGInventors: Bipin Rajendran, Thomas Happ, Hsiang-Lan Lung, Min Yang
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Publication number: 20130309782Abstract: An example embodiment disclosed is a process for fabricating a phase change memory cell. The method includes forming a bottom electrode, creating a pore in an insulating layer above the bottom electrode, depositing piezoelectric material in the pore, depositing phase change material in the pore proximate the piezoelectric material, and forming a top electrode over the phase change material. Depositing the piezoelectric material in the pore may include conforming the piezoelectric material to at least one wall defining the pore such that the piezoelectric material is deposited between the phase change material and the wall. The conformal deposition may be achieved by chemical vapor deposition (CVD) or by atomic layer deposition (ALD).Type: ApplicationFiled: July 24, 2013Publication date: November 21, 2013Applicants: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE, INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Catherine A. Dubourdieu, Martin M. Frank, Bipin Rajendran, Alejandro G. Schrott
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Patent number: 8589320Abstract: A neuromorphic system includes a plurality of synapse blocks electrically connected to a plurality of neuron circuit blocks. The plurality of synapse blocks includes a plurality of neuromorphic circuits. Each neuromorphic circuit includes a field effect transistor in a diode configuration electrically connected to variable resistance material, where the variable resistance material provides a programmable resistance value. Each neuromorphic circuit also includes a first junction electrically connected to the variable resistance material and an output of one or more of the neuron circuit blocks, and a second junction electrically connected to the field effect transistor and an input of one or more of the neuron circuit blocks.Type: GrantFiled: July 13, 2012Date of Patent: November 19, 2013Assignee: International Business Machines CorporationInventors: Matthew J. Breitwisch, Chung Hon Lam, Dharmendra S. Modha, Bipin Rajendran
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Patent number: 8586960Abstract: An integrated circuit includes a substrate including isolation regions, a first conductive line formed in the substrate between isolation regions, and a vertical diode formed in the substrate. The integrated circuit includes a contact coupled to the vertical diode and a memory element coupled to the contact. The first conductive line provides a portion of the vertical diode.Type: GrantFiled: June 19, 2008Date of Patent: November 19, 2013Assignees: International Business Machines Corporation, Macronix International Co., Ltd., Qimonda AGInventors: Thomas Happ, Hsiang-Lan Lung, Bipin Rajendran, Min Yang
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Publication number: 20130299768Abstract: Memory cell structures for phase change memory. An example memory cell structure comprising includes a bottom electrode comprised of electrically conducting material, and phase change material disposed above the bottom electrode. A layer of thermally insulating material is disposed, at least partially, between the bottom electrode and the phase change material. The thermally insulating material is comprised of Tantalum Oxide. A top electrode is comprised of electrically conducting material.Type: ApplicationFiled: July 22, 2013Publication date: November 14, 2013Applicant: International Business Machines CorporationInventors: Matthew J. BrightSky, Roger W. Cheek, Chung H. Lam, Eric A. Joseph, Bipin Rajendran, Alejandro G. Schrott, Yu Zhu
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Patent number: 8559217Abstract: An example embodiment disclosed is a phase change memory cell. The memory cell includes a phase change material and a transducer positioned proximate the phase change material. The phase change material is switchable between at least an amorphous state and a crystalline state. The transducer is configured to activate when the phase change material is changed from the amorphous state to the crystalline state. In a particular embodiment, the transducer is ferroelectric material.Type: GrantFiled: December 10, 2010Date of Patent: October 15, 2013Assignee: International Business Machines CorporationInventors: Catherine A. Dubourdieu, Martin M. Frank, Bipin Rajendran, Alejandro G. Schrott
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Patent number: 8558210Abstract: A resistive non-volatile memory cell with a bipolar junction transistor (BJT) access device formed in conjunction with the entire memory cell. The memory cell includes a substrate acting as a collector, a semiconductor base layer acting as a base, and a semiconductor emitter layer acting as an emitter. Additionally, metal plugs and the phase change memory element are formed above the BJT access device while the emitter, metal plugs, and phase change memory element are contained within an insulating region. In one embodiment of the invention, a spacer layer is formed and the emitter layer is contained within the protective spacer layer. The spacer layer is contained within the insulating region.Type: GrantFiled: April 18, 2012Date of Patent: October 15, 2013Assignee: International Business Machines CorporationInventors: Bipin Rajendran, Tak H. Ning, Chung H. Lam
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Patent number: 8536675Abstract: A memory cell structure and method for forming the same. The method includes forming a pore within a dielectric layer. The pore is formed over the center of an electrically conducting bottom electrode. The method includes depositing a thermally insulating layer along at least one sidewall of the pore. The thermally insulating layer isolates heat from phase change current to the volume of the pore. In one embodiment phase change material is deposited within the pore and the volume of the thermally insulating layer. In another embodiment a pore electrode is formed within the pore and the volume of the thermally insulating layer, with the phase change material being deposited above the pore electrode. The method also includes forming an electrically conducting top electrode above the phase change material.Type: GrantFiled: February 1, 2012Date of Patent: September 17, 2013Assignee: International Business Machines CorporationInventors: Matthew J. Breitwisch, Roger W. Cheek, Eric A. Joseph, Chung H. Lam, Bipin Rajendran, Alejandro G. Schrott, Yu Zhu