Patents by Inventor Biraja Prasad Dash
Biraja Prasad Dash has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10979052Abstract: In some examples, a level shifter circuit comprises: a first transistor pair cascoded at a first input node; a second transistor pair cascoded at a second input node, wherein the first and transistor pairs couple at a first node, a second node, a third node, and a fourth node; a third transistor pair coupled to the first transistor pair at the first and the third nodes, wherein the third transistor pair is configured to generate a first bipolar clock signal; a fourth transistor pair coupled to the second transistor pair at the second and the fourth nodes, wherein the fourth transistor pair is configured to generate a second bipolar clock signal; and a clock generation circuit coupled to the first node, the second node, the third node, and the fourth node.Type: GrantFiled: January 28, 2020Date of Patent: April 13, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Biraja Prasad Dash, Ravinthiran Balasingam, Dimitar Trifonov
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Publication number: 20200162075Abstract: In some examples, a level shifter circuit comprises: a first transistor pair cascoded at a first input node; a second transistor pair cascoded at a second input node, wherein the first and transistor pairs couple at a first node, a second node, a third node, and a fourth node; a third transistor pair coupled to the first transistor pair at the first and the third nodes, wherein the third transistor pair is configured to generate a first bipolar clock signal; a fourth transistor pair coupled to the second transistor pair at the second and the fourth nodes, wherein the fourth transistor pair is configured to generate a second bipolar clock signal; and a clock generation circuit coupled to the first node, the second node, the third node, and the fourth node.Type: ApplicationFiled: January 28, 2020Publication date: May 21, 2020Inventors: Biraja Prasad DASH, Ravinthiran BALASINGAM, Dimitar TRIFONOV
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Patent number: 10630245Abstract: A six phase capacitively coupled chopper amplifier. Two phases provide a zeroing phase to zero the feedback capacitors and set the input common mode value. Two phases provide a passive transfer of an input charge from the input capacitors to the zeroed feedback capacitors. The final two phases are chopping and amplification phases. The zeroing phases address the input common mode without the need for biasing resistors. The passive transfer phases resolve the glitching that occurs if the feedback capacitors have to be recharged on each cycle of the chopping clock. Resolving the glitching and the charge time allows the frequency of the amplifier to increase.Type: GrantFiled: September 10, 2018Date of Patent: April 21, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Dimitar Trifonov, Biraja Prasad Dash, Ravinthiran Balasingam
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Publication number: 20200106390Abstract: A circuit, comprising an input chopper configured to receive an input signal, a differential amplifier having an input coupled to an output of the input chopper, a current mode chopping circuit coupled to an output of the differential amplifier, and a first current mirror bias transistor pair coupled between a voltage supply and the current mode chopping circuit.Type: ApplicationFiled: December 3, 2019Publication date: April 2, 2020Inventors: Ravinthiran BALASINGAM, Dimitar TRIFONOV, Biraja Prasad DASH
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Patent number: 10587267Abstract: In some examples, a level shifter circuit comprises: a first transistor pair cascoded at a first input node; a second transistor pair cascoded at a second input node, wherein the first and transistor pairs couple at a first node, a second node, a third node, and a fourth node; a third transistor pair coupled to the first transistor pair at the first and the third nodes, wherein the third transistor pair is configured to generate a first bipolar clock signal; a fourth transistor pair coupled to the second transistor pair at the second and the fourth nodes, wherein the fourth transistor pair is configured to generate a second bipolar clock signal; and a clock generation circuit coupled to the first node, the second node, the third node, and the fourth node.Type: GrantFiled: May 3, 2019Date of Patent: March 10, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Biraja Prasad Dash, Ravinthiran Balasingam, Dimitar Trifonov
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Patent number: 10530302Abstract: A circuit, comprising an input chopper configured to receive an input signal, a differential amplifier having an input coupled to an output of the input chopper, a current mode chopping circuit coupled to an output of the differential amplifier, and a first current mirror bias transistor pair coupled between a voltage supply and the current mode chopping circuit.Type: GrantFiled: July 23, 2018Date of Patent: January 7, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Ravinthiran Balasingam, Dimitar Trifonov, Biraja Prasad Dash
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Patent number: 10483920Abstract: Embodiments relate to a chopped amplifier system where a ripple reduction filter placed outside of a main signal path is disclosed. The chopped amplifier system includes a chopped amplifier having an input terminal and an output terminal, where the input terminal receives an input signal and the output terminal provides an output signal including a ripple that is based on an offset voltage of the chopped amplifier. The ripple reduction filter is placed in a feedback loop path that receives a portion of the chopped amplifier's output signal and provides a feedback signal to the chopped amplifier that reduces the ripple at the output of the chopped amplifier. The ripple reduction filter includes a digital controller and other circuits that can handle large disturbances such as large signal slew rate events and large common-mode steps without reducing the effectiveness of the ripple reduction filter in reducing the ripple.Type: GrantFiled: May 17, 2018Date of Patent: November 19, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Tony Ray Larson, Dimitar Trifonov Trifonov, Biraja Prasad Dash
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Publication number: 20190260379Abstract: In some examples, a level shifter circuit comprises: a first transistor pair cascoded at a first input node; a second transistor pair cascoded at a second input node, wherein the first and transistor pairs couple at a first node, a second node, a third node, and a fourth node; a third transistor pair coupled to the first transistor pair at the first and the third nodes, wherein the third transistor pair is configured to generate a first bipolar clock signal; a fourth transistor pair coupled to the second transistor pair at the second and the fourth nodes, wherein the fourth transistor pair is configured to generate a second bipolar clock signal; and a clock generation circuit coupled to the first node, the second node, the third node, and the fourth node.Type: ApplicationFiled: May 3, 2019Publication date: August 22, 2019Inventors: Biraja Prasad DASH, Ravinthiran BALASINGAM, Dimitar TRIFONOV
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Patent number: 10326451Abstract: In some examples, a level shifter circuit comprises: a first transistor pair cascoded at a first input node; a second transistor pair cascoded at a second input node, wherein the first and transistor pairs couple at a first node, a second node, a third node, and a fourth node; a third transistor pair coupled to the first transistor pair at the first and the third nodes, wherein the third transistor pair is configured to generate a first bipolar clock signal; a fourth transistor pair coupled to the second transistor pair at the second and the fourth nodes, wherein the fourth transistor pair is configured to generate a second bipolar clock signal; and a clock generation circuit coupled to the first node, the second node, the third node, and the fourth node.Type: GrantFiled: August 13, 2018Date of Patent: June 18, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Biraja Prasad Dash, Ravinthiran Balasingam, Dimitar Trifonov
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Publication number: 20190158091Abstract: In some examples, a level shifter circuit comprises: a first transistor pair cascoded at a first input node; a second transistor pair cascoded at a second input node, wherein the first and transistor pairs couple at a first node, a second node, a third node, and a fourth node; a third transistor pair coupled to the first transistor pair at the first and the third nodes, wherein the third transistor pair is configured to generate a first bipolar clock signal; a fourth transistor pair coupled to the second transistor pair at the second and the fourth nodes, wherein the fourth transistor pair is configured to generate a second bipolar clock signal; and a clock generation circuit coupled to the first node, the second node, the third node, and the fourth node.Type: ApplicationFiled: August 13, 2018Publication date: May 23, 2019Inventors: Biraja Prasad DASH, Ravinthiran BALASINGAM, Dimitar TRIFONOV
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Publication number: 20190158035Abstract: A six phase capacitively coupled chopper amplifier. Two phases provide a zeroing phase to zero the feedback capacitors and set the input common mode value. Two phases provide a passive transfer of an input charge from the input capacitors to the zeroed feedback capacitors. The final two phases are chopping and amplification phases. The zeroing phases address the input common mode without the need for biasing resistors. The passive transfer phases resolve the glitching that occurs if the feedback capacitors have to be recharged on each cycle of the chopping clock. Resolving the glitching and the charge time allows the frequency of the amplifier to increase.Type: ApplicationFiled: September 10, 2018Publication date: May 23, 2019Inventors: Dimitar TRIFONOV, Biraja Prasad DASH, Ravinthiran BALASINGAM
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Publication number: 20190158026Abstract: A circuit, comprising an input chopper configured to receive an input signal, a differential amplifier having an input coupled to an output of the input chopper, a current mode chopping circuit coupled to an output of the differential amplifier, and a first current mirror bias transistor pair coupled between a voltage supply and the current mode chopping circuit.Type: ApplicationFiled: July 23, 2018Publication date: May 23, 2019Inventors: Ravinthiran BALASINGAM, Dimitar TRIFONOV, Biraja Prasad DASH
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Publication number: 20180337639Abstract: Embodiments relate to a chopped amplifier system where a ripple reduction filter placed outside of a main signal path is disclosed. The chopped amplifier system includes a chopped amplifier having an input terminal and an output terminal, where the input terminal receives an input signal and the output terminal provides an output signal including a ripple that is based on an offset voltage of the chopped amplifier. The ripple reduction filter is placed in a feedback loop path that receives a portion of the chopped amplifier's output signal and provides a feedback signal to the chopped amplifier that reduces the ripple at the output of the chopped amplifier. The ripple reduction filter includes a digital controller and other circuits that can handle large disturbances such as large signal slew rate events and large common-mode steps without reducing the effectiveness of the ripple reduction filter in reducing the ripple.Type: ApplicationFiled: May 17, 2018Publication date: November 22, 2018Inventors: Tony Ray Larson, Dimitar Trifonov Trifonov, Biraja Prasad Dash
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Patent number: 10003306Abstract: Embodiments relate to a chopped amplifier system where a ripple reduction filter placed outside of a main signal path is disclosed. The chopped amplifier system includes a chopped amplifier having an input terminal and an output terminal, where the input terminal receives an input signal and the output terminal provides an output signal including a ripple that is based on an offset voltage of the chopped amplifier. The ripple reduction filter is placed in a feedback loop path that receives a portion of the chopped amplifier's output signal and provides a feedback signal to the chopped amplifier that reduces the ripple at the output of the chopped amplifier. The ripple reduction filter includes a digital controller and other circuits that can handle large disturbances such as large signal slew rate events and large common-mode steps without reducing the effectiveness of the ripple reduction filter in reducing the ripple.Type: GrantFiled: March 23, 2017Date of Patent: June 19, 2018Assignee: Texas Instruments IncorporatedInventors: Tony Ray Larson, Dimitar Trifonov Trifonov, Biraja Prasad Dash