Patents by Inventor Bishop Chapman Brock

Bishop Chapman Brock has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8370517
    Abstract: A data processing network and method for conserving energy in which an initial negotiation between a network server and a switch to which the server is connected is performed to establish an initial operating frequency of the server-switch link. An effective data rate of the server is determined based on network traffic at the server. Responsive to determining that the effective data rate is materially different than the current operating frequency, a subsequent negotiation is performed to establish a modified operating frequency where the modified operating frequency is closer to the effective data rate than the initial operating frequency. The determination of the effective date rate and the contingent initiation of a subsequent negotiation may be repeated periodically during the operating of the network. In one embodiment, the initial and subsequent negotiation are compliant with the IEEE 802.3 standard.
    Type: Grant
    Filed: September 27, 2001
    Date of Patent: February 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Patrick Joseph Bohrer, Bishop Chapman Brock, Elmootazbellah Nabil Elnozahy, Ramakrishnan Rajamony, Freeman Leigh Rawson, III
  • Patent number: 6886106
    Abstract: A method and apparatus for providing a dynamically alterable output clock from an input clock based on the value of an integer, where the integer can be modified continuously. The invention also provides a sample cycle output which is an enable pulse, having the width of the input clock cycle, that is asserted one or two input clock cycles prior to the rising edge alignment of the input and output clocks, that acts as a rising edge alignment enable signal, maintaining a one-to-one correspondence between the sample cycle assertions and rising edge alignment events, regardless of the dynamic changes in the value of the integer.
    Type: Grant
    Filed: October 16, 2001
    Date of Patent: April 26, 2005
    Assignee: International Business Machines Corporation
    Inventors: Bishop Chapman Brock, Gary Dale Carpenter, Amanda Christine Caswell, Eric William MacDonald, Timothy Joe Rubidoux
  • Patent number: 6836849
    Abstract: A method and controller for managing power and performance of a multiprocessor (MP) system is described. The controller receives sensor data corresponding to physical parameters within the MP system. The controller also receives quality of service and policy parameters corresponding to the MP system. The quality of service parameters define commitments to customers for utilization of the MP system. The policy parameters correspond to operation limits on inputs and outputs of the MP system. The operation input limits relate to the cost and availability of power or individual processor availability. The operation output limits relate to the amount of heat, acoustic noise levels, EMC levels, etc. that the individual or group of processors in the MP system are allowed to generate in a particular environment. A controller receives the physical parameters, the quality of service parameters and policy parameters and determines performance goals for the MP system and processors within the MP system.
    Type: Grant
    Filed: April 5, 2001
    Date of Patent: December 28, 2004
    Assignee: International Business Machines Corporation
    Inventors: Bishop Chapman Brock, Harm Peter Hofstee, Mark A. Johnson, Thomas Walter Keller, Jr., Kevin John Nowka
  • Publication number: 20040194087
    Abstract: A method and system in which client requests to a multi-server, local area network (server cluster) are accumulated during discrete time intervals (batching periods), but not processed immediately. The servers are initialized to a low power state. At the end of a batching period or upon occurrence of some other specified event, the server cluster selects one or more servers to process the accumulated requests. The selected servers are then powered on and the requests are distributed to the powered servers for processing and response generation. After all requests have been responded to, the server cluster typically powers down the servers such that servers are actively powered only during the periods when batched requests are being processed. During times when a server cluster's request loading is sufficiently light, the response periods will be significantly shorter than the batching periods.
    Type: Application
    Filed: April 11, 2002
    Publication date: September 30, 2004
    Applicant: International Business Machines Corporation
    Inventors: Bishop Chapman Brock, Elmootazbellah Nabil Elnozahy, thomas Walter Keller,, Ramakrishnan Rajamony, Freeman Leigh Rawson
  • Patent number: 6662251
    Abstract: A system in which bus signals are selectively modified to effectively isolate desired bus agents from the bus. The selective modification of bus signals may be determined from a stored table (permission table) indicating permitted and prohibited bus transaction initiator/target pairs. The permission table may be located in a dedicated device, such as a programmable logic array or application specific integrated circuit. Alternatively, the permission table may be integrated into the bus arbiter. The permission table may be used to provide a unique 1-bit signal to each bus agent indicating whether the corresponding bus agent is permitted to receive transactions from the current bus master. The permission bit may be routed to external gating circuitry associated with each bus agent. The gating circuitry may receive one or more bus control signals and may modify the control signals depending upon the state of the permission bit.
    Type: Grant
    Filed: March 26, 2001
    Date of Patent: December 9, 2003
    Assignee: International Business Machines Corporation
    Inventors: Bishop Chapman Brock, Gary Dale Carpenter
  • Patent number: 6601149
    Abstract: A system for and method of monitoring memory transactions in a data processing system are disclosed. The method includes defining a set of memory transaction attributes with a monitoring system and detecting, on a data processing system connected to the monitoring system, memory transactions that match the defined set of memory transaction attributes. The number of detected memory transactions occurring during a specified duration are then displayed in a graphical format. In one embodiment, the data processing system comprises a non-uniform memory architecture (NUMA) system comprising a set of nodes. In this embodiment, the detected transactions comprise transactions passing through a switch connecting the nodes of the NUMA system. The set of memory transaction attributes may include memory transaction type information, node information, and transaction direction information.
    Type: Grant
    Filed: December 14, 1999
    Date of Patent: July 29, 2003
    Assignee: International Business Machines Corporation
    Inventors: Bishop Chapman Brock, Eli Chiprout, Elmootazbellah Nabil Elnozahy, Ramakrishnan Rajamony, Freeman Leigh Rawson, III, Ronald Lynn Rockhold
  • Publication number: 20030079151
    Abstract: The distribution of power dissipation within cluster systems is managed by a combination of inter-node and intra-node policies. The inter-node policy consists of subdividing the nodes within the cluster into three sets, namely the “Operational” set, the “Standby” set and the “Hibernating” set. Nodes in the Operational set continue to function and execute computation in response to user requests. Nodes in the Standby set have their processors in the low-energy standby mode and are ready to resume the computation immediately. Nodes in the Hibernating set are turned off to further conserve energy, and they need a relatively longer time to resume operation than nodes in the Standby set. The inter-node policy further distributes the computation among nodes in the Operational set such that each node in the set consumes the same amount of energy.
    Type: Application
    Filed: October 18, 2001
    Publication date: April 24, 2003
    Applicant: International Business Machines Corporation
    Inventors: Patrick Joseph Bohrer, Bishop Chapman Brock, Elmootazbellah Nabil Elnozahy, Thomas Walter Keller, Michael David Kistler, Ramakrishnan Rajamony
  • Publication number: 20030074595
    Abstract: A method and apparatus for providing a dynamically alterable output clock from an input clock based on the value of an integer, where the integer can be modified continuously. The invention also provides a sample cycle output which is an enable pulse, having the width of the input clock cycle, that is asserted one or two input clock cycles prior to the rising edge alignment of the input and output clocks, that acts as a rising edge alignment enable signal, maintaining a one-to-one correspondence between the sample cycle assertions and rising edge alignment events, regardless of the dynamic changes in the value of the integer.
    Type: Application
    Filed: October 16, 2001
    Publication date: April 17, 2003
    Applicant: International Business Machines Corporation
    Inventors: Bishop Chapman Brock, Gary Dale Carpenter, Amanda Christine Caswell, Eric William MacDonald, Timothy Joe Rubidoux
  • Publication number: 20030074464
    Abstract: A data processing network and method for conserving energy in which an initial negotiation between a network server and a switch to which the server is connected is performed to establish an initial operating frequency of the server-switch link. An effective data rate of the server is determined based on network traffic at the server. Responsive to determining that the effective data rate is materially different than the current operating frequency, a subsequent negotiation is performed to establish a modified operating frequency where the modified operating frequency is closer to the effective data rate than the initial operating frequency. The determination of the effective date rate and the contingent initiation of a subsequent negotiation may be repeated periodically during the operating of the network. In one embodiment, the initial and subsequent negotiation are compliant with the IEEE 802.3 standard.
    Type: Application
    Filed: September 27, 2001
    Publication date: April 17, 2003
    Applicant: International Business Machines Corporation
    Inventors: Patrick Joseph Bohrer, Bishop Chapman Brock, Elmootazbellah Nabil Elnozahy, Ramakrishnan Rajamony, Freeman Leigh Rawson
  • Publication number: 20030004948
    Abstract: A system and method of retrieving data from a disk includes determining the network transfer rate of a network connection between a client and a server. A first portion of the requested data is retrieved from the disk responsive to a data request received by the server from the client via a network connection and transmission of the first portion of data to the client via the network is initiated. The time required to transmit the first portion of data to the client is calculated based upon the network transfer rate and a determination of when to retrieve a subsequent portion of the requested data from disk is made based, in part, on whether the calculated time is expired. The determination of when to retrieve subsequent portions of data from disk may be further based on a desire to minimize a system parameter such as memory usage or disk energy consumption and heat dissipation.
    Type: Application
    Filed: June 29, 2001
    Publication date: January 2, 2003
    Applicant: International Business Machines Corporation
    Inventors: Patrick Joseph Bohrer, Bishop Chapman Brock, Elmootazbellah Nabil Elnozahy, Ramakrishnan Rajamony
  • Patent number: 6499028
    Abstract: A performance monitor configured to count memory transactions and to issue an interrupt to the computer system if the monitor detects a specified number of transactions associated with a particular segment of the physical address space of the system. The monitor includes an interface suitable for coupling to an interconnect network of a computer system and configured to extract physical address information from a transaction traversing the interconnect network, a translation module adapted for associating the extracted physical address with one of a plurality of memory blocks and, in response thereto, incrementing a memory block counter corresponding to the memory block, and an interrupt unit configured to assert an interrupt if the block counter exceeds a predetermined value. The interface unit is configurable to selectively monitor either incoming or outgoing transactions and the translation unit preferably includes a plurality of region filters each comprising one or more of the memory blocks.
    Type: Grant
    Filed: March 31, 1999
    Date of Patent: December 24, 2002
    Assignee: International Business Machines Corporation
    Inventors: Bishop Chapman Brock, Eli Chiprout, Elmootazbellah Nabil Elnozahy, David Brian Glasco, Ramakrishnan Rajamony, Freeman Leigh Rawson, III, Ronald Lynn Rockhold
  • Patent number: 6473085
    Abstract: A method and system for optimizing image quality while operating an interactive graphics application within a data processing system. First, the image rendering speed for each of the rendering modes available within the interactive graphics application are assessed. Upon initial operation of the interactive graphics system, a default rendering mode is activated. During operation of the interactive graphics application, the processing load imposed on the data processing system is monitored and utilized as a user activity metric. The active rendering mode is updated in accordance with the user activity metric, such that the speed of the selected rendering mode varies inversely with the current processing load.
    Type: Grant
    Filed: December 17, 1999
    Date of Patent: October 29, 2002
    Assignee: International Business Machines Corporation
    Inventors: Bishop Chapman Brock, Eli Chiprout, Elmootazebllah Nabil Elinozahy, Ramakrishnan Rajamony, Freeman Leigh Rawson, III, Ronald Lynn Rockhold
  • Publication number: 20020147932
    Abstract: A method and controller for managing power and performance of a multiprocessor (MP) system is described. The controller receives sensor data corresponding to physical parameters within the MP system. The controller also receives quality of service and policy parameters corresponding to the MP system. The quality of service parameters define commitments to customers for utilization of the MP system. The policy parameters correspond to operation limits on inputs and outputs of the MP system. The operation input limits relate to the cost and availability of power or individual processor availability. The operation output limits relate to the amount of heat, acoustic noise levels, EMC levels, etc. that the individual or group of processors in the MP system are allowed to generate in a particular environment. A controller receives the physical parameters, the quality of service parameters and policy parameters and determines performance goals for the MP system and processors within the MP system.
    Type: Application
    Filed: April 5, 2001
    Publication date: October 10, 2002
    Applicant: International Business Machines Corporation
    Inventors: Bishop Chapman Brock, Harm Peter Hofstee, Mark A. Johnson, Thomas Walter Keller, Kevin John Nowka
  • Publication number: 20020138677
    Abstract: A system in which bus signals are selectively modified to effectively isolate desired bus agents from the bus. The selective modification of bus signals may be determined from a stored table (permission table) indicating permitted and prohibited bus transaction initiator/target pairs. The permission table may be located in a dedicated device, such as a programmable logic array or application specific integrated circuit. Alternatively, the permission table may be integrated into the bus arbiter. The permission table may be used to provide a unique 1-bit signal to each bus agent indicating whether the corresponding bus agent is permitted to receive transactions from the current bus master. The permission bit may be routed to external gating circuitry associated with each bus agent. The gating circuitry may receive one or more bus control signals and may modify the control signals depending upon the state of the permission bit.
    Type: Application
    Filed: March 26, 2001
    Publication date: September 26, 2002
    Applicant: International Business Machines Corporation
    Inventors: Bishop Chapman Brock, Gary Dale Carpenter
  • Patent number: 6442654
    Abstract: A system and method for providing in-server caching of shared data involves a server program that defines a server cache in RAM of a server machine and stores a selected file in the server cache. If a cached file is modified through the file system interface of the operating system of the server machine, the operating system automatically issues an upcall to the server program, the upcall identifying the modified file. In response to receipt of the upcall, the server program removes the modified file from the server cache. In one embodiment, the server program responds to a client request requiring access to a requested file by obtaining the requested file from the server cache if the server cache contains that file. Otherwise, the server program calls the operating system to obtain the requested file and then adds that file to the server cache as a cached file. The server program then generates a result based on the requested file and transmits the result to the remote data processing system.
    Type: Grant
    Filed: December 10, 1999
    Date of Patent: August 27, 2002
    Assignee: International Business Machines Corporation
    Inventors: Bishop Chapman Brock, Eli Chiprout, Elmootazbellah Nabil Elnozahy, Ramakrishnan Rajamony, Freeman Leigh Rawson, III, Ronald Lynn Rockhold
  • Patent number: 6421775
    Abstract: A data processing system includes a plurality of processing nodes that each contain at least one processor and data storage. The plurality of processing nodes are coupled together by a system interconnect. The data processing system further includes a configuration utility residing in data storage within at least one of the plurality of processing nodes. The configuration utility selectively configures the plurality of processing nodes into either a single non-uniform memory access (NUMA) system or into multiple independent data processing systems through communication via the system interconnect.
    Type: Grant
    Filed: June 17, 1999
    Date of Patent: July 16, 2002
    Assignee: International Business Machines Corporation
    Inventors: Bishop Chapman Brock, David Brian Glasco, James Lyle Peterson, Ramakrishnan Rajamony, Ronald Lynn Rockhold
  • Patent number: 6349394
    Abstract: A performance monitor for a computer system that includes an interface, a filter module, and an address mapping module. The interface is suitable for coupling to an interconnect network of the computer system. The interconnect network links a local node of the system with at least one remote node of the system. The interface is configured to extract physical address information from a transaction traversing the interconnect network. The filter module associates the physical address with one of several memory blocks, where each memory block comprises a contiguous portion of the system's physical address space. The address mapping module associates the identified memory block with at least one range of virtual addresses associated with at least one of a plurality of concurrently executing programs and increments each of a set of access counters. The association between the selected memory block and the access counters is facilitated by a pointer field corresponding to the memory block.
    Type: Grant
    Filed: March 31, 1999
    Date of Patent: February 19, 2002
    Assignee: International Business Machines Corporation
    Inventors: Bishop Chapman Brock, Eli Chiprout, Elmootazbellah Nabil Elnozahy, David Brian Glasco, Ramakrishnan Rajamony, Freeman Leigh Rawson, III, Ronald Lynn Rockhold