Abstract: Provided are an electronic device for a network control terminal and a network node, and a method for the electronic device. The electronic device for a network control terminal comprises processing circuitry configured to set a first condition concerning a beam-forming capacity of a network node for determining the network node capable of serving as a relay node, and to generate control signaling of indication information comprising the first condition for indicating the network node served by the network control terminal.

Abstract: The present disclosure provides electronic device and method for interleaved multiple access communication. An electronic device for an interleaved multiple access control terminal comprises a processing circuit, which is configured to acquire information about interleaved multiple access communication between a receiving apparatus and a transmitting apparatus; determine configuration parameters for the transmitting apparatus based on the information, the configuration parameters comprising operation parameters of an interleaver of the transmitting apparatus, the interleaver being used to distinguish the transmitting apparatus from other transmitting apparatus; and provide the determined configuration parameters to the transmitting apparatus, so that the transmitting apparatus is configured with the transmitting parameters for communicating with the receiving apparatus.

Abstract: The present invention provides an apparatus and a method in a radio communications system. The apparatus in a radio communications system comprises an estimation unit and a statistics collection unit. The estimation unit is used for estimating a signal receiving strength of each of multiple transmission positions, compared with a signal transmission strength of each of one or more possible transmission positions of a first-type node of a to-be-test communications system on a transmission resource block. The statistics collection unit is used for collecting, according the estimation result, statistics on power space distribution of the first-type node of the to-be-tested communications system.

Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor layer, forming a plurality of semiconductor fins on a surface of the semiconductor layer extending in parallel to each other along a first direction parallel to the surface of the semiconductor layer, and forming a plurality of gate electrodes comprising longitudinal portions extending parallel to the semiconductor fins along the first direction.

Abstract: The present invention provides an apparatus and a method in a radio communications system. The apparatus in a radio communications system comprises an estimation unit and a statistics collection unit. The estimation unit is used for estimating a signal receiving strength of each of multiple transmission positions, compared with a signal transmission strength of each of one or more possible transmission positions of a first-type node of a to-be-test communications system on a transmission resource block. The statistics collection unit is used for collecting, according the estimation result, statistics on power space distribution of the first-type node of the to-be-tested communications system.

Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor layer, forming a plurality of semiconductor fins on a surface of the semiconductor layer extending in parallel to each other along a first direction parallel to the surface of the semiconductor layer, and forming a plurality of gate electrodes comprising longitudinal portions extending parallel to the semiconductor fins along the first direction.

Abstract: Embodiments of the present invention are a filtering element, a filtering equipment and a water circulation cleaning system. In an embodiment, a filtering element includes a filtering screen and filter particles adhered to one side of the filtering screen, sizes of the filter particles being gradually increased in a direction from the one side to the other side of the filtering screen. Meanwhile, there also provides a filtering equipment including the abovementioned filtering element and a water circulation cleaning system including the abovementioned filtering equipment.

Abstract: A semiconductor device including a semiconductor layer, a plurality of semiconductor fins formed on a surface of the semiconductor layer and a plurality of gate electrodes formed over the surface of the semiconductor layer is provided. The semiconductor fins extend in parallel to each other along a first direction parallel to the surface of the semiconductor layer and have a first height in a second direction that is perpendicular to the first direction, and the gate electrodes comprise longitudinal portions extending parallel to the semiconductor fins along the first direction and, in particular, having a second height in the second direction lower than the first height.

Abstract: A semiconductor device including a semiconductor layer, a plurality of semiconductor fins formed on a surface of the semiconductor layer and a plurality of gate electrodes formed over the surface of the semiconductor layer is provided. The semiconductor fins extend in parallel to each other along a first direction parallel to the surface of the semiconductor layer and have a first height in a second direction that is perpendicular to the first direction, and the gate electrodes comprise longitudinal portions extending parallel to the semiconductor fins along the first direction and, in particular, having a second height in the second direction lower than the first height.

Abstract: An apparatus and a method in a radio communications system. The apparatus in the radio communications system includes an estimation unit and a statistics collection unit. The estimation unit is used for estimating a signal receiving strength of each of multiple transmission positions, compared with a signal transmission strength of each of one or more possible transmission positions of a first-type node of a to-be-test communications system on a transmission resource block. The statistics collection unit is used for collecting, according the estimation result, statistics on power space distribution of the first-type node of the to-be-tested communications system.

Abstract: Methods for fabricating integrated circuits and components thereof are provided. In accordance with an exemplary embodiment, a method for fabricating an integrated circuit is provided. The method includes providing a semiconductor substrate with a first gate structure and a second gate structure and a shallow trench isolation region outside of the first and second gate structures, depositing a mask on the first gate structure, and depositing a protection layer on the shallow trench isolation region to embed a STI protective cap.

Abstract: An apparatus and a method in a radio communications system. The apparatus in the radio communications system includes an estimation unit and a statistics collection unit. The estimation unit is used for estimating a signal receiving strength of each of multiple transmission positions, compared with a signal transmission strength of each of one or more possible transmission positions of a first-type node of a to-be-test communications system on a transmission resource block. The statistics collection unit is used for collecting, according the estimation result, statistics on power space distribution of the first-type node of the to-be-tested communications system.

Abstract: In sophisticated semiconductor devices, transistors may be formed on the basis of an efficient strain-inducing mechanism by using an embedded strain-inducing semiconductor alloy. The strain-inducing semiconductor material may be provided as a graded material with a smooth strain transfer into the neighboring channel region in order to reduce the number of lattice defects and provide enhanced strain conditions, which in turn directly translate into superior transistor performance. The superior architecture of the graded strain-inducing semiconductor material may be accomplished by selecting appropriate process parameters during the selective epitaxial growth process without contributing to additional process complexity.

Abstract: A complementary metal oxide semiconductor (CMOS) circuit incorporating a substrate and a gate wire over the substrate. The substrate comprises an n-type field effect transistor (n-FET) region, a p-type field effect transistor (p-FET) region and an isolation region disposed between the n-FET and p-FET regions. The gate wire comprises an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate. A first conformal insulator covers the gate wire and a second conformal insulator is on the first conformal insulator positioned over the p-FET gate without extending laterally over the n-FET gate. Straining regions for producing different types of strain are formed in recess etched into the n-FET and p-FET regions of the substrate.

Abstract: In sophisticated semiconductor devices, transistors may be formed on the basis of an efficient strain-inducing mechanism by using an embedded strain-inducing semiconductor alloy. The strain-inducing semiconductor material may be provided as a graded material with a smooth strain transfer into the neighboring channel region in order to reduce the number of lattice defects and provide enhanced strain conditions, which in turn directly translate into superior transistor performance. The superior architecture of the graded strain-inducing semiconductor material may be accomplished by selecting appropriate process parameters during the selective epitaxial growth process without contributing to additional process complexity.

Abstract: A PCB includes a number of insulation layers, a number of circuit layers, a signal-interfering component, and a signal-sensitive component. The circuit layers and the insulation layers are stacked alternately. The circuit layers include at least two first circuit layers, a second circuit layer, and a ground layer. The ground layer has a first side and a second side facing away the first side. The first circuit layers are positioned near the first side and include an outmost first circuit layer and at least one inner first circuit layer positioned between the outmost first circuit layer and the ground layer. The second circuit layer is positioned near the second side. The signal-interfering component is positioned on the outmost first circuit layer. The signal-sensitive component is positioned on the second circuit layer. Each inner first circuit layer defines a copper-remove area corresponding to an orthogonal projection of the signal-interfering component thereon.

Abstract: A method of manufacturing a complementary metal oxide semiconductor (CMOS) circuit, in which the method includes a reactive ion etch (RIE) of a CMOS circuit substrate that forms recesses, the CMOS circuit substrate including: an n-type field effect transistor (n-FET) region; a p-type field effect transistor (p-FET) region; an isolation region disposed between the n-FET and p-FET regions; and a gate wire comprising an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate, in which the recesses are formed adjacent to sidewalls of a reduced thickness; growing silicon germanium (SiGe) in the recesses; depositing a thin insulator layer on the CMOS circuit substrate; masking at least the p-FET region; removing the thin insulator layer from an unmasked n-FET region and an unmasked portion of the isolation region; etching the CMOS circuit substrate with hydrogen chloride (HCl) to remove the SiGe from the recesses in the n-FET region; and g

Abstract: An NMOS transistor is formed with improved manufacturability. An embodiment includes forming N-type doped embedded silicon germanium containing carbon (eSiGe:C) in source/drain regions of a substrate, and amorphizing the eSiGe:C. The use of eSiGe:C provides a reduction in extension silicon and dopant loss, improved morphology, increased wafer throughput, improved short channel control, and reduced silicide to source/drain contact resistance.

Abstract: A method of manufacturing a complementary metal oxide semiconductor (CMOS) circuit, in which the method includes a reactive ion etch (RIE) of a CMOS circuit substrate that forms recesses, the CMOS circuit substrate including: an n-type field effect transistor (n-FET) region; a p-type field effect transistor (p-FET) region; an isolation region disposed between the n-FET and p-FET regions; and a gate wire comprising an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate, in which the recesses are formed adjacent to sidewalls of a reduced thickness; growing silicon germanium (SiGe) in the recesses; depositing a thin insulator layer on the CMOS circuit substrate; masking at least the p-FET region; removing the thin insulator layer from an unmasked n-FET region and an unmasked portion of the isolation region; etching the CMOS circuit substrate with hydrogen chloride (HCl) to remove the SiGe from the recesses in the n-FET region; and g

Abstract: A PCB includes a number of insulation layers, a number of circuit layers, a signal-interfering component, and a signal-sensitive component. The circuit layers and the insulation layers are stacked alternately. The circuit layers include at least two first circuit layers, a second circuit layer, and a ground layer. The ground layer has a first side and a second side facing away the first side. The first circuit layers are positioned near the first side and include an outmost first circuit layer and at least one inner first circuit layer positioned between the outmost first circuit layer and the ground layer. The second circuit layer is positioned near the second side. The signal-interfering component is positioned on the outmost first circuit layer. The signal-sensitive component is positioned on the second circuit layer. Each inner first circuit layer defines a copper-remove area corresponding to an orthogonal projection of the signal-interfering component thereon.