Patents by Inventor Bo-Huan HSIN

Bo-Huan HSIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250028893
    Abstract: The present disclosure describes an example layout and method for cell placement in an integrated circuit (IC) layout design. The layout includes a first semiconductor structure having a first channel with a first channel width and a second semiconductor structure having a second channel with a second channel width different from the first channel width. The first and second channels can be in contact with each other. The method includes disposing a first diffusion region in a layout area and disposing a second diffusion region in the layout area. The first diffusion region can have a first diffusion region width and the second diffusion region can have a second diffusion region width different from the first diffusion region width.
    Type: Application
    Filed: July 21, 2023
    Publication date: January 23, 2025
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Bo-Huan HSIN, Ying-Han CHIOU, Shih-Cheng CHANG
  • Publication number: 20240405127
    Abstract: A semiconductor device includes a first transistor, a first via contact, a second transistor and a second via contact. The first transistor includes a channel and a gate electrode. The first via contact is disposed on the gate electrode of the first transistor, and corresponds in position to the channel of the first transistor. The second transistor includes a channel and a gate electrode. The second via contact is disposed on the gate electrode of the second transistor, and corresponds in position to the channel of the second transistor. A distance between the second via contact and the channel of the second transistor is smaller than a distance between the first via contact and the channel of the first transistor.
    Type: Application
    Filed: June 2, 2023
    Publication date: December 5, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Bo-Huan HSIN, Ying-Han CHIOU, Ming-Yen TSAI
  • Publication number: 20240405126
    Abstract: A semiconductor device and a manufacturing method of the semiconductor device are provided. The semiconductor device includes a source region, a drain region, a channel region and a plurality of fins. The channel region is located between the source region and the drain region, and the fins pass through the source region, the drain region and the channel region, wherein a number of the fins located in the source region and the drain region and a number of the fins located in the channel region are not equal.
    Type: Application
    Filed: June 2, 2023
    Publication date: December 5, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Huan HSIN, Ying-Han CHIOU, Ming-Yen TSAI
  • Publication number: 20240387304
    Abstract: A semiconductor structure with a protective ring and the method of forming the same are provided. The semiconductor structure may comprise an integrated circuit die and an encapsulant encircling the integrated circuit die in a top down view. The integrated circuit die may comprise a substrate having an electrical device, an interconnect structure on the substrate and electrically coupled to the electrical device, a seal ring in the interconnect structure and encircling the electrical device in the top down view, and a protective ring at least partially embedded in the substrate. The protective ring may encircle the seal ring in a top down view and may comprise a material different from a material of the substrate.
    Type: Application
    Filed: May 17, 2023
    Publication date: November 21, 2024
    Inventors: Bo-Huan Hsin, Ying-Han Chiou
  • Publication number: 20240047562
    Abstract: A method includes forming a semiconductor fin upwardly extending from a substrate; forming a gate strip extending across the semiconductor fin; forming source/drain regions on the semiconductor fin and at opposite sides of the gate strip; forming a gate spacer on a sidewall of the gate strip; forming a film layer on the gate spacer; performing an etching process on the gate strip to break the gate strip into a first gate structure and a second gate structure, the etching process further consuming the gate spacer while remains the film layer; forming an isolation structure interposing the first and second gate structures.
    Type: Application
    Filed: August 5, 2022
    Publication date: February 8, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Bo-Huan HSIN, Ying-Han CHIOU