Abstract: Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to a common source line. The methods include receiving a third voltage at a gate of the second transistor and a gate of the fourth transistor that may cause them to operate in cutoff mode. The methods may include receiving a fourth voltage at a gate of the first transistor. The fourth voltage may cause a change in a charge storage layer included in the first transistor.

Abstract: Method of operating a catalytic steam-hydrocarbon reformer where the steam flow rate at which carbon forms on the inner wall of a catalyst-containing reformer tube is determined, and the steam flow rate to the catalytic steam-hydrocarbon reformer is controlled responsive to the determined steam flow rate at which carbon forms on the inner wall of the catalyst-containing reformer tube.

Abstract: An adsorption vessel comprising a packed bed region of adsorbent particles contiguously arranged, comprising a perforated adsorbent particles, a gas separation process using the perforated adsorbent particles, and methods for making the perforated adsorbent particles. The perforated adsorbent particles each comprise an adsorbent material where the perforated adsorbent particles each have at least 10 channels extending through the particle. The equivalent diameter of the channels may range from 0.05 mm to 1.5 mm, and the void fraction of the channels may range from 0.05 to 0.5.

Abstract: An adsorption vessel comprising a packed bed region of adsorbent particles contiguously arranged comprising a perforated adsorbent particles, a gas separation process using the perforated adsorbent particles, and methods for making the perforated adsorbent particles. The perforated adsorbent particles each comprise an adsorbent material where the perforated adsorbent particles each have at least 10 channels extending through the particle. The equivalent diameter of the channels may range from 0.05 mm to 1.5 mm, and the void fraction of the channels may range from 0.05 to 0.5.

Abstract: Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to a common source line. The methods include receiving a third voltage at a gate of the second transistor and a gate of the fourth transistor that may cause them to operate in cutoff mode. The methods may include receiving a fourth voltage at a gate of the first transistor. The fourth voltage may cause a change in a charge storage layer included in the first transistor.

Abstract: An adsorption vessel comprising a packed bed region of adsorbent particles contiguously arranged, comprising a perforated adsorbent particles, a gas separation process using the perforated adsorbent particles, and methods for making the perforated adsorbent particles. The perforated adsorbent particles each comprise an adsorbent material where the perforated adsorbent particles each have at least 10 channels extending through the particle. The equivalent diameter of the channels may range from 0.05 mm to 1.5 mm, and the void fraction of the channels may range from 0.05 to 0.5.

Abstract: Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to a common source line. The methods include receiving a third voltage at a gate of the second transistor and a gate of the fourth transistor that may cause them to operate in cutoff mode. The methods may include receiving a fourth voltage at a gate of the first transistor. The fourth voltage may cause, via Fowler-Nordheim tunneling, a change in a charge storage layer included in the first transistor.

Abstract: A method for generating and check-controlling a network identity identification code in a network electronic identity is provided for the establishment of a unified network identity management and service ecosystem that effectively protects the network application security and identity information privacy of citizens. A server performs initialization and generates and distributes random numbers while receiving and auditing a request to generate a network identity identification code from a client. If the client passes the audit, encryption coding is performed and a network identity identification code is generated and sent to a network electronic identification card through the client. The network electronic identification card performs check processing of the network identity identification code, and feeds back a result to the server. The server stores the network identity identification code into a database, and informs the user.

Abstract: A memory structure including a memory array of a plurality of memory cells arranged in rows and columns, the plurality of memory cells including a pair of adjacent memory cells in a row of the memory array, wherein the pair of adjacent memory cells include a single, shared source-line through which each of the memory cells in the pair of adjacent memory cells is coupled to a voltage source. Methods of operating a memory including the memory structure are also described.

Abstract: Methods are described for warming a sample that contains a cell or tissue, wherein the method heats the sample at a warming rate of at least about 1×106° C. and/or that increase the functional survival of the cell or tissue upon warming. The warming can be done using a laser that emits infrared wavelength light. Also described are systems and devices for rapid warming and cooling of samples.

Abstract: Methods for diagnosis of Kawasaki disease (KD) are disclosed. In particular, the invention relates to the use of biomarkers for aiding diagnosis, prognosis, and treatment of KD, and to a panel of biomarkers that can be used to distinguish KD from febrile illness.

Abstract: Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to a common source line. The methods include receiving a third voltage at a gate of the second transistor and a gate of the fourth transistor that may cause them to operate in cutoff mode. The methods may include receiving a fourth voltage at a gate of the first transistor. The fourth voltage may cause, via Fowler-Nordheim tunneling, a change in a charge storage layer included in the first transistor.

Abstract: An embodiment of a method of integration of a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming a pad dielectric layer of a MOS device above a first region of a substrate; forming a channel of the memory device from a thin film of semiconducting material overlying a surface above a second region of the substrate, the channel connecting a source and drain of the memory device; forming a patterned dielectric stack overlying the channel above the second region, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer; simultaneously removing the sacrificial top layer from the second region of the substrate, and the pad dielectric layer from the first region of the substrate; and simultaneously forming a gate dielectric layer above the first region of the substrate and a blocking dielectric layer above the charge-trapping layer.

Abstract: A memory structure including a memory array of a plurality of memory cells arranged in rows and columns, the plurality of memory cells including a pair of adjacent memory cells in a row of the memory array, wherein the pair of adjacent memory cells include a single, shared source-line through which each of the memory cells in the pair of adjacent memory cells is coupled to a voltage source. Methods of operating a memory including the memory structure are also described.

Abstract: Methods of ONO integration into MOS flow are provided. In one embodiment, the method comprises: (i) forming a pad dielectric layer above a MOS device region of a substrate; and (ii) forming a patterned dielectric stack above a non-volatile device region of the substrate, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer, the charge-trapping layer comprising multiple layers including a first nitride layer formed on the tunnel layer and a second nitride layer, wherein the first nitride layer is oxygen rich relative to the second nitride layer. Other embodiments are also described.

Abstract: Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to a common source line. The methods include receiving a third voltage at a gate of the second transistor and a gate of the fourth transistor that may cause them to operate in cutoff mode. The methods may include receiving a fourth voltage at a gate of the first transistor. The fourth voltage may cause, via Fowler-Nordheim tunneling, a change in a charge storage layer included in the first transistor.

Abstract: The present invention relates to a method for generating and check-controlling a network identity identification code in a network electronic identity. The method comprises: a server performing initialization and performing generation and distribution of random numbers; receiving and auditing a request to generate the network identity identification code from a client; if the auditing is passed, performing encryption coding and generating a network identity identification code, and then sending the network identity identification code to a network electronic identification card through the client; the network electronic identification card performing the check processing of a network identity identification code, and feeding back a result to the server; the server storing the network identity identification code into a database, and informing the user.

Abstract: A method for sending uplink scheduling grant signaling and a base station, applied in an Advanced Long Term Evolution (LTE-A) system, the method includes: a base station, according to a number of clusters occupied with non-consecutive resource allocation by a Physical Uplink Shared Channel (PUSCH) of a scheduled user equipment in a component carrier, configuring at least one uplink scheduling grant signaling for the user equipment, wherein each uplink scheduling grant signaling indicates an allocation of resource for one or two clusters occupied by the PUSCH; and the base station allocating a Physical Downlink Control Channel (PDCCH) for each uplink scheduling grant signaling, and sending the uplink scheduling grant signaling to the user equipment. The flexibility of the resource allocation in the case of multiple clusters is enhanced, meanwhile the reliability of transmission of the scheduling grant signaling is ensured.

Abstract: A system and a method for allocating Sounding Reference Signal (SRS) resources are provided in the present invention, the method includes: an e-Node-B (eNB) allocating a SRS bandwidth with 4n Resource Blocks (RBs) to a terminal, and equally dividing a time domain sequence of a SRS into t portions in the SRS bandwidth; the eNB configuring a time domain RePetition Factor (RPF) used by the UE, and the eNB configuring the UE to use one or more cyclic shifts in L cyclic shifts for each UE; then the eNB notifying the UE of a value of the time domain RPF, a location of a used frequency comb and a used cyclic shift by signaling, wherein n is a positive integer; the RPF satisfies a following condition: 48 × n RPF can be exactly divided by 12; t is an integer by which 48 × n RPF can be exactly divided; and L?t.