Patents by Inventor Bogdan Govoreanu

Bogdan Govoreanu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10490738
    Abstract: In one aspect, a resistive switching memory device includes a first electrode and a second electrode having interposed therebetween a first inner region and a second inner region, where the first and second inner regions contacting each other. The first inner region includes one or more metal oxide layers and the second inner region consists of a plurality of layers, where each of the layers of the second inner region is an insulating, a semi-insulating or a semiconducting layer. The second inner region comprises one or more layers having a stoichiometric or off-stoichiometric composition of a material selected from the group consisting of SiGex, SiNx, AlOx, MgOx, AINx, HfOx, HfSiOx, ZrOx, ZrSiOx, GdAlOx, DyScOx, TaOx and combinations thereof. The second inner region comprises one or more silicon-containing layers, such that one of the one or more silicon-containing layers contacts the first inner region.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: November 26, 2019
    Assignee: IMEC vzw
    Inventor: Bogdan Govoreanu
  • Publication number: 20170358742
    Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to memory or storage devices based on resistive switching, and to methods of making and using such devices. In one aspect, a resistive switching memory device includes a first electrode and a second electrode having interposed therebetween a first inner region and a second inner region, where the first and second inner regions contacting each other. The first inner region includes one or more metal oxide layers and the second inner region consists of a plurality of layers, where each of the layers of the second inner region is an insulating, a semi-insulating or a semiconducting layer. The second inner region comprises one or more layers having a stoichiometric or off-stoichiometric composition of a material selected from the group consisting of SiGex, SiNx, AlOx, MgOx, AlNx, SiNx, HfOx, HfSiOx, ZrOx, ZrSiOx, GdAlOx, DyScOx, TaOx and combinations thereof.
    Type: Application
    Filed: June 16, 2017
    Publication date: December 14, 2017
    Inventor: Bogdan Govoreanu
  • Patent number: 9786795
    Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to selector devices for memory devices having a resistance switching element, particularly resistive random access memory (RRAM) devices. In one aspect, a selector device includes a first barrier structure comprising a first metal and a first semiconductor or a first low bandgap dielectric material, and a second barrier structure comprising a second metal and a second semiconductor or a second low bandgap dielectric material. The selector device additionally includes an insulator interposed between the first semiconductor or the first low bandgap dielectric material and the second semiconductor or the second low bandgap dielectric material. The first barrier structure, the insulator, and the second barrier structure are stacked to form a metal/semiconductor or low bandgap dielectric/insulator/semiconductor or low bandgap dielectric/metal structure.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: October 10, 2017
    Assignees: IMEC VZW, Katholieke Universiteit Leuven
    Inventors: Bogdan Govoreanu, Christoph Adelmann, Leqi Zhang, Malgorzata Jurczak
  • Patent number: 9595668
    Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to memory devices having a resistance switching element, and to methods of operating such memory devices. In one aspect, a memory cell includes a first electrode and a second electrode formed of one of a metallic material or a semiconducting material. The memory cell additionally includes a resistance switching element formed between the first electrode and the second electrode. The memory cell additionally includes a tunnel rectifier formed between the resistance-switching element and the first electrode. The tunnel rectifier includes a multi-layer tunnel stack comprising at least two dielectric layers each having a dielectric constant (ki), a conduction band offset (?i), and a thickness, wherein one of the dielectric layers has a higher dielectric constant, a lower conduction band offset and a higher thickness compared to any other dielectric layer of the multi-layer tunnel stack.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: March 14, 2017
    Assignee: IMEC vzw
    Inventor: Bogdan Govoreanu
  • Publication number: 20150097187
    Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to selector devices for memory devices having a resistance switching element, particularly resistive random access memory (RRAM) devices. In one aspect, a selector device includes a first barrier structure comprising a first metal and a first semiconductor or a first low bandgap dielectric material, and a second barrier structure comprising a second metal and a second semiconductor or a second low bandgap dielectric material. The selector device additionally includes an insulator interposed between the first semiconductor or the first low bandgap dielectric material and the second semiconductor or the second low bandgap dielectric material. The first barrier structure, the insulator, and the second barrier structure are stacked to form a metal/semiconductor or low bandgap dielectric/insulator/semiconductor or low bandgap dielectric/metal structure.
    Type: Application
    Filed: October 7, 2014
    Publication date: April 9, 2015
    Inventors: Bogdan GOVOREANU, Christoph ADELMANN, Leqi ZHANG, Malgorzata JURCZAK
  • Publication number: 20140367631
    Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to memory devices having a resistance switching element, and to methods of operating such memory devices. In one aspect, a memory cell includes a first electrode and a second electrode formed of one of a metallic material or a semiconducting material. The memory cell additionally includes a resistance switching element formed between the first electrode and the second electrode. The memory cell additionally includes a tunnel rectifier formed between the resistance-switching element and the first electrode. The tunnel rectifier includes a a multi-layer tunnel stack comprising at least two dielectric layers each having a dielectric constant (ki), a conduction band offset (?i), and a thickness, wherein one of the dielectric layers has a higher dielectric constant, a lower conduction band offset and a higher thickness compared to any other dielectric layer of the multi-layer tunnel stack.
    Type: Application
    Filed: June 16, 2014
    Publication date: December 18, 2014
    Inventor: Bogdan GOVOREANU
  • Patent number: 8441064
    Abstract: A method for manufacturing a non-volatile memory device is described. The method comprises growing a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored. A non-volatile memory device is also described. In the non-volatile memory device, the interpoly/blocking dielectric comprises a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored, the siliconoxide consuming material having consumed at least part of the upper layer.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: May 14, 2013
    Assignee: IMEC
    Inventors: Bogdan Govoreanu, Stefan De Gendt, Sven Van Elshocht, Tom Schram
  • Patent number: 8119511
    Abstract: A non-volatile memory device having a control gate on top of the second dielectric (interpoly or blocking dielectric), at least a bottom layer of the control gate in contact with the second dielectric being constructed in a material having a predefined high work-function and showing a tendency to reduce its work-function when in contact with a group of certain high-k materials after full device fabrication. At least a top layer of the second dielectric, separating the bottom layer of the control gate from the rest of the second dielectric, is constructed in a predetermined high-k material, chosen outside the group for avoiding a reduction in the work-function of the material of the bottom layer of the control gate. In the manufacturing method, the top layer is created in the second dielectric before applying the control gate.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: February 21, 2012
    Assignee: IMEC
    Inventors: Bogdan Govoreanu, HongYu Yu, Hag-Ju Cho
  • Publication number: 20110291179
    Abstract: A method for manufacturing a non-volatile memory device is described. The method comprises growing a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored. A non-volatile memory device is also described. In the non-volatile memory device, the interpoly/blocking dielectric comprises a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored, the siliconoxide consuming material having consumed at least part of the upper layer.
    Type: Application
    Filed: August 11, 2011
    Publication date: December 1, 2011
    Applicant: IMEC
    Inventors: Bogdan Govoreanu, Stefan De Gendt, Sven Van Elshocht, Tom Schram
  • Patent number: 8021948
    Abstract: A method for manufacturing a non-volatile memory device is described. The method comprises growing a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored. A non-volatile memory device is also described. In the non-volatile memory device, the interpoly/blocking dielectric comprises a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored, the siliconoxide consuming material having consumed at least part of the upper layer.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: September 20, 2011
    Assignee: IMEC
    Inventors: Bogdan Govoreanu, Stefan De Gendt, Sven Van Elshocht, Tom Schram
  • Publication number: 20110183509
    Abstract: A non-volatile memory device having a control gate on top of the second dielectric (interpoly or blocking dielectric), at least a bottom layer of the control gate in contact with the second dielectric being constructed in a material having a predefined high work-function and showing a tendency to reduce its work-function when in contact with a group of certain high-k materials after full device fabrication. At least a top layer of the second dielectric, separating the bottom layer of the control gate from the rest of the second dielectric, is constructed in a predetermined high-k material, chosen outside the group for avoiding a reduction in the work-function of the material of the bottom layer of the control gate. In the manufacturing method, the top layer is created in the second dielectric before applying the control gate.
    Type: Application
    Filed: April 5, 2011
    Publication date: July 28, 2011
    Applicants: Interuniversitair Microelektronica Centrum vzw (IMEC), Samsung Electronics Co. Ltd.
    Inventors: Bogdan Govoreanu, HongYu Yu, Hag-Ju Cho
  • Patent number: 7626226
    Abstract: Non-volatile memory devices are disclosed. In a first example non-volatile memory device, programming and erasing of the memory device is performed through the same insulating barrier without the use of a complex symmetrical structure. In the example device, programming is accomplished by tunneling negative charge carriers from a charge supply region to a charge storage region. Further in the example device, erasing is accomplished by tunneling positive carriers from the charge supply region to the charge storage region. In a second example non-volatile memory device, a charge storage region with spatially distributed charge storage region is included. Such a charge storage region may be implemented in the first example memory device or may be implemented in other memory devices. In the second example device, programming is accomplished by tunneling negative charge carriers from a charge supply region to the charge storage region.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: December 1, 2009
    Assignee: Interuniversitair Microelektronica Centrum (IMEC)
    Inventor: Bogdan Govoreanu
  • Publication number: 20090166715
    Abstract: A method for manufacturing a non-volatile memory device is described. The method comprises growing a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored. A non-volatile memory device is also described. In the non-volatile memory device, the interpoly/blocking dielectric comprises a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored, the siliconoxide consuming material having consumed at least part of the upper layer.
    Type: Application
    Filed: December 18, 2008
    Publication date: July 2, 2009
    Applicant: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC)
    Inventors: Bogdan Govoreanu, Stefan De Gendt, Sven Van Elshocht, Tom Schram
  • Publication number: 20090134453
    Abstract: A non-volatile memory device having a control gate on top of the second dielectric (interpoly or blocking dielectric), at least a bottom layer of the control gate in contact with the second dielectric being constructed in a material having a predefined high work-function and showing a tendency to reduce its work-function when in contact with a group of certain high-k materials after full device fabrication. At least a top layer of the second dielectric, separating the bottom layer of the control gate from the rest of the second dielectric, is constructed in a predetermined high-k material, chosen outside the group for avoiding a reduction in the work-function of the material of the bottom layer of the control gate. In the manufacturing method, the top layer is created in the second dielectric before applying the control gate.
    Type: Application
    Filed: November 21, 2008
    Publication date: May 28, 2009
    Applicants: Interuniversitair Microelektronica Centrum vzw (IMEC), Samsung Electronics Co. Ltd.
    Inventors: Bogdan Govoreanu, HongYu Yu, Hag-ju Cho
  • Publication number: 20080185632
    Abstract: Non-volatile memory devices are disclosed. In a first example non-volatile memory device, programming and erasing of the memory device is performed through the same insulating barrier without the use of a complex symmetrical structure. In the example device, programming is accomplished by tunneling negative charge carriers from a charge supply region to a charge storage region. Further in the example device, erasing is accomplished by tunneling positive carriers from the charge supply region to the charge storage region. In a second example non-volatile memory device, a charge storage region with spatially distributed charge storage region is included. Such a charge storage region may be implemented in the first example memory device or may be implemented in other memory devices. In the second example device, programming is accomplished by tunneling negative charge carriers from a charge supply region to the charge storage region.
    Type: Application
    Filed: October 29, 2007
    Publication date: August 7, 2008
    Applicant: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC)
    Inventors: Bogdan Govoreanu, Maarten Rosmeulen, Pieter Blomme
  • Patent number: 7332768
    Abstract: Non-volatile memory devices are disclosed. In a first example non-volatile memory device, programming and erasing of the memory device is performed through the same insulating barrier without the use of a complex symmetrical structure. In the example device, programming is accomplished by tunneling negative charge carriers from a charge supply region to a charge storage region. Further in the example device, erasing is accomplished by tunneling positive carriers from the charge supply region to the charge storage region. In a second example non-volatile memory device, a charge storage region with spatially distributed charge storage region is included. Such a charge storage region may be implemented in the first example memory device or may be implemented in other memory devices. In the second example device, programming is accomplished by tunneling negative charge carriers from a charge supply region to the charge storage region.
    Type: Grant
    Filed: March 2, 2006
    Date of Patent: February 19, 2008
    Assignee: Interuniversitair Microelektronica Centrum (IMEC)
    Inventors: Bogdan Govoreanu, Maarten Rosmeulen, Pieter Blomme
  • Publication number: 20060175656
    Abstract: Non-volatile memory devices are disclosed. In a first example non-volatile memory device, programming and erasing of the memory device is performed through the same insulating barrier without the use of a complex symmetrical structure. In the example device, programming is accomplished by tunneling negative charge carriers from a charge supply region to a charge storage region. Further in the example device, erasing is accomplished by tunneling positive carriers from the charge supply region to the charge storage region. In a second example non-volatile memory device, a charge storage region with spatially distributed charge storage region is included. Such a charge storage region may be implemented in the first example memory device or may be implemented in other memory devices. In the second example device, programming is accomplished by tunneling negative charge carriers from a charge supply region to the charge storage region.
    Type: Application
    Filed: March 2, 2006
    Publication date: August 10, 2006
    Applicant: Interuniversitair Microelektronica Centrum (IMEC vzw)
    Inventors: Bogdan Govoreanu, Maarten Rosmeulen, Pieter Blomme
  • Patent number: 7026686
    Abstract: An insulating barrier extending between a first conductive region and a second conductive region is disclosed. The insulating barrier is provided for tunnelling charge carriers from the first to the second region, the insulating barrier comprising a first portion contacting the first region and a second portion contacting the first portion and extending towards the second region, the first portion being substantially thinner than the second portion, the first portion being constructed in a first dielectric and the second portion being constructed in a second dielectric different from the first dielectric, the first dielectric having a lower dielectric constant than the second dielectric.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: April 11, 2006
    Assignee: Interuniversitair Microelektronica Centrum (IMEC vzw)
    Inventors: Pieter Blomme, Bogdan Govoreanu, Maarten Rosmeulen
  • Publication number: 20050017288
    Abstract: An insulating barrier extending between a first conductive region and a second conductive region is disclosed. The insulating barrier is provided for tunnelling charge carriers from the first to the second region, the insulating barrier comprising a first portion contacting the first region and a second portion contacting the first portion and extending towards the second region, the first portion being substantially thinner than the second portion, the first portion being constructed in a first dielectric and the second portion being constructed in a second dielectric different from the first dielectric, the first dielectric having a lower dielectric constant than the second dielectric.
    Type: Application
    Filed: June 28, 2004
    Publication date: January 27, 2005
    Inventors: Pieter Blomme, Bogdan Govoreanu, Maarten Rosmeulen
  • Patent number: 6784484
    Abstract: An insulating barrier extending between a first conductive region and a second conductive region is disclosed. The insulating barrier is provided for tunnelling charge carriers from the first to the second region, the insulating barrier comprising a first portion contacting the first region and a second portion contacting the first portion and extending towards the second region, the first portion being substantially thinner than the second portion, the first portion being constructed in a first dielectric and the second portion being constructed in a second dielectric different from the first dielectric, the first dielectric having a lower dielectric constant than the second dielectric.
    Type: Grant
    Filed: April 25, 2002
    Date of Patent: August 31, 2004
    Assignee: Interuniversitair Micoroelektronica Centrum (IMEC, vzw)
    Inventors: Pieter Blomme, Bogdan Govoreanu, Maarten Rosmeulen