Abstract: An initial condition (IC) behavior module is described for use in a hardware definition language simulation system which operates in two phases. In the first phase, the IC module sets an initial logic condition onto a user-selected node which is to be monitored. The IC module will release the initial condition and then test the node value to determine if the simulation system is able to resolve the node. Alternatively, the IC module may release the node if a user-defined IC time period passes. In the second phase, the IC module monitors the node and reports an error message if the simulated node value becomes unacceptable.

Abstract: A method and system for producing property forms for use in creating design schematics for an integrated circuit using computer-aided design apparatus wherein property forms are produced using a unique sophisticated cell library. The library includes a parameter database that includes base level component description format parameters which provide all of the information that is needed for creating the parameter labels, prompts, data boxes, selectors, etc. for property forms for each logic gate defined in a cell library and for a plurality of operating modes. This allows a single cell library to be used in the creation of a design schematic while permitting parameters of all logic gate instances to be specified at any one of three different design levels or modes, including a mode in which only the drive strength of n-channel type devices is specified, a mode in which the drive strengths of N and P type devices are specified, and a mode in which all of the parameters of all devices are specified.

Abstract: A method and system for producing property forms for use in creating design schematics for an integrated circuit using computer-aided design apparatus wherein property forms are produced using a unique sophisticated cell library. The library includes a parameter database that includes base level component description format parameters which provide all of the information that is needed for creating the parameter labels, prompts, data boxes, selectors, etc. for property forms for each logic gate defined in a cell library and for a plurality of operating modes. This allows a single cell library to be used in the creation of a design schematic while permitting parameters of all logic gate instances to be specified at any one of three different design levels or modes, including a mode in which only the drive strength of n-channel type devices is specified, a mode in which the drive strengths of N and P type devices are specified, and a mode in which all of the parameters of all devices are specified.

Abstract: A musical article of furniture, here jewelry armoire (10') which includes a pivotal lid (38') for activating and deactivating a musical movement (19). Mechanical spring wound musical movement (19) is attached to a supporting surface (14') which in turn is attached to lid (38'). Musical movement (19) includes a rotating shaft, also serving as the winding shaft (21), protruding through a top surface of supporting surface (14'). An ornament (34) is affixed to the shaft and the shaft is decoratively finished. Musical movement (19) is provided with a stop-and-start mechanism which includes a control arm (22') being positioned and configured to interfere with the back of housing (39') such that the mechanism will be activated when lid (38') is opened and will shut off when the lid is closed.

Abstract: A musical article of furniture, here jewelry chest (10) which includes at least one slidable drawer (12) for storage of articles and for activating and deactivating a musical movement (19). Mechanical spring wound musical movement (19) is attached to a supporting surface (14) of the housing (11) of chest (10) and has a rotating shaft, also serving as the winding shaft (21), protruding through an outside surface of chest housing (11). An ornament (34) is affixed to the shaft and the shaft is decoratively finished. Musical movement (19) is provided with a stop-and-start mechanism which includes a control arm (22) being positioned and configured to interfere with the back (13) of upper drawer (12) such that the mechanism will be activated when the drawer is opened and will shut off when the drawer is closed.

Abstract: A polysilicon layer is provided with a p-type impurity, and masked with an oxide mask to define a p-type region of the polysilicon layer. A second impurity is then provided into first unmasked regions of the polysilicon layer. A second oxide mask is deposited and anisotropically etched to form spacers adjacent to the first oxide mask. The spacers define two diffusion barrier regions of the polysilicon layer adjacent to the p-type region. An n-type impurity is then provided into second unmasked regions of the polysilicon layer to form two n-type regions adjacent the diffusion barrier regions. The diffusion barrier regions prevent cross diffusion of the p-type and the n-type impurities within the polysilicon layer, while also being of sufficient dimensions to permit normal p/n operations.

Abstract: A polysilicon layer is provided with a p-type impurity, and masked with an oxide mask to define a p-type region of the polysilicon layer. A second impurity is then provided into first unmasked regions of the polysilicon layer. A second oxide mask is deposited and anisotropically etched to form spacers adjacent to the first oxide mask. The spacers define two diffusion barrier regions of the polysilicon layer adjacent to the p-type region. An n-type impurity is then provided into second unmasked regions of the polysilicon layer to form two n-type regions adjacent the diffusion barrier regions. The diffusion barrier regions prevent cross diffusion of the p-type and the n-type impurities within the polysilicon layer, while also being of sufficient dimensions to permit normal p/n operations.

Abstract: A polysilicon layer is provided with a p-type impurity, and masked with an oxide mask to define a p-type region of the polysilicon layer. A second impurity is then provided into first unmasked regions of the polysilicon layer. A second oxide mask is deposited and anisotropically etched to form spacers adjacent to the first oxide mask. The spacers define two diffusion barrier regions of the polysilicon layer adjacent to the p-type region. An n-type impurity is then provided into second unmasked regions of the polysilicon layer to form two n-type regions adjacent the diffusion barrier regions. The diffusion barrier regions prevent cross diffusion of the p-type and the n-type impurities within the polysilicon layer, while also being of sufficient dimensions to permit normal p/n operations.