Patents by Inventor Bon-Young Koo

Bon-Young Koo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10727348
    Abstract: A semiconductor device may include first and second fins formed side by side on a substrate, a first elevated doped region formed on the first fin and having a first doping concentration of impurities, a second elevated doped region formed on the second fin, and a first bridge connecting the first elevated doped region and the second elevated doped region to each other. Methods of manufacturing such a semiconductor device are also disclosed.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: July 28, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seok-Hoon Kim, Bon-Young Koo, Nam-Kyu Kim, Woo-Bin Song, Byeong-Chan Lee, Su-Jin Jung
  • Patent number: 10685957
    Abstract: A semiconductor device includes an active fin on a substrate, a gate structure on the active fin, a gate spacer structure on a sidewall of the gate structure, and a source/drain layer on at least a portion of the active fin adjacent the gate spacer structure. The gate spacer structure includes a wet etch stop pattern, an oxygen-containing silicon pattern, and an outgas sing prevention pattern sequentially stacked.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: June 16, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Hyun Choi, Yong-Suk Tak, Gi-Gwan Park, Bon-Young Koo, Ki-Yeon Park, Won-Oh Seo
  • Patent number: 10541127
    Abstract: A material layer, a semiconductor device including the material layer, and methods of forming the material layer and the semiconductor device are provided herein. A method of forming a SiOCN material layer may include supplying a silicon source onto a substrate, supplying a carbon source onto the substrate, supplying an oxygen source onto the substrate, supplying a nitrogen source onto the substrate, and supplying hydrogen onto the substrate. When a material layer is formed according to a method of the present inventive concepts, a material layer having a high tolerance to wet etching and/or good electric characteristics may be formed, and may even be formed when the method is performed at a low temperature.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: January 21, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-suk Tak, Gi-gwan Park, Jin-bum Kim, Bon-young Koo, Ki-yeon Park, Tae-jong Lee
  • Patent number: 10529555
    Abstract: A method of forming a SiOCN material layer, a material layer stack, a semiconductor device, a method of fabricating a semiconductor device, and a deposition apparatus, the method of forming a SiOCN material layer including providing a substrate; providing a silicon precursor onto the substrate; providing an oxygen reactant onto the substrate; providing a first carbon precursor onto the substrate; providing a second carbon precursor onto the substrate; and providing a nitrogen reactant onto the substrate, wherein the first carbon precursor and the second carbon precursor are different materials.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: January 7, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-suk Tak, Tae-jong Lee, Bon-young Koo, Ki-yeon Park, Sung-hyun Choi
  • Patent number: 10460927
    Abstract: A method of forming a SiOCN material layer, a material layer stack, a semiconductor device, a method of fabricating a semiconductor device, and a deposition apparatus, the method of forming a SiOCN material layer including providing a substrate; providing a silicon precursor onto the substrate; providing an oxygen reactant onto the substrate; providing a first carbon precursor onto the substrate; providing a second carbon precursor onto the substrate; and providing a nitrogen reactant onto the substrate, wherein the first carbon precursor and the second carbon precursor are different materials.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: October 29, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong-suk Tak, Tae-jong Lee, Bon-young Koo, Ki-yeon Park, Sung-hyun Choi
  • Publication number: 20190287797
    Abstract: A method of forming a SiOCN material layer, a material layer stack, a semiconductor device, a method of fabricating a semiconductor device, and a deposition apparatus, the method of forming a SiOCN material layer including providing a substrate; providing a silicon precursor onto the substrate; providing an oxygen reactant onto the substrate; providing a first carbon precursor onto the substrate; providing a second carbon precursor onto the substrate; and providing a nitrogen reactant onto the substrate, wherein the first carbon precursor and the second carbon precursor are different materials.
    Type: Application
    Filed: May 24, 2019
    Publication date: September 19, 2019
    Inventors: Yong-suk TAK, Tae-jong LEE, Bon-young KOO, Ki-yeon PARK, Sung-hyun CHOI
  • Patent number: 10388791
    Abstract: A semiconductor device may include first and second fins formed side by side on a substrate, a first elevated doped region formed on the first fin and having a first doping concentration of impurities, a second elevated doped region formed on the second fin, and a first bridge connecting the first elevated doped region and the second elevated doped region to each other. Methods of manufacturing such a semiconductor device are also disclosed.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: August 20, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seok-Hoon Kim, Bon-Young Koo, Nam-Kyu Kim, Woo-Bin Song, Byeong-Chan Lee, Su-Jin Jung
  • Publication number: 20190221663
    Abstract: A semiconductor device may include first and second fins formed side by side on a substrate, a first elevated doped region formed on the first fin and having a first doping concentration of impurities, a second elevated doped region formed on the second fin, and a first bridge connecting the first elevated doped region and the second elevated doped region to each other. Methods of manufacturing such a semiconductor device are also disclosed.
    Type: Application
    Filed: March 28, 2019
    Publication date: July 18, 2019
    Inventors: Seok-Hoon KIM, Bon-Young KOO, Nam-Kyu KIM, Woo-Bin SONG, Byeong-Chan LEE, Su-Jin JUNG
  • Patent number: 10164030
    Abstract: A semiconductor device may include a substrate including an NMOS region and a PMOS region, and having a protrusion pattern; first and second gate structures respectively formed on the NMOS region and the PMOS region of the substrate, crossing the protrusion pattern, and extending along a first direction that is parallel to an upper surface of the substrate; first and second source/drain regions formed on both sides of the first and second gate structures; and first and second contact plugs respectively formed on the first and second source/drain regions, wherein the first contact plug and the second contact plug are asymmetric. Methods of manufacturing are also provided.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: December 25, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-bum Kim, Chul-sung Kim, Deok-han Bae, Bon-young Koo
  • Patent number: 10147723
    Abstract: A semiconductor device includes a substrate, a first active fin and a second active fin on the substrate, respectively, a plurality of first epitaxial layers on the first active fin and on the second active fin, respectively, a plurality of second epitaxial layers on the plurality of first epitaxial layers, a bridge layer connecting the plurality of second epitaxial layers to each other, and a third epitaxial layer on the bridge layer.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: December 4, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-Hoon Kim, Jin-Bum Kim, Kwan-Heum Lee, Byeong-Chan Lee, Cho-Eun Lee, Jin-Hee Han, Bon-Young Koo
  • Patent number: 10141427
    Abstract: A semiconductor device includes a gate pattern on a substrate, a multi-channel active pattern under the gate pattern to cross the gate pattern and having a first region not overlapping the gate pattern and a second region overlapping the gate pattern, a diffusion layer in the multi-channel active pattern along the outer periphery of the first region and including an impurity having a concentration, and a liner on the multi-channel active pattern, the liner extending on lateral surfaces of the first region and not extending on a top surface of the first region. Related fabrication methods are also described.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: November 27, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-In Choi, Gyeom Kim, Hong-Sik Yoon, Bon-Young Koo, Wook-Je Kim
  • Publication number: 20180301452
    Abstract: A semiconductor device includes an active fin on a substrate, a gate structure on the active fin, a gate spacer structure on a sidewall of the gate structure, and a source/drain layer on at least a portion of the active fin adjacent the gate spacer structure. The gate spacer structure includes a wet etch stop pattern, an oxygen-containing silicon pattern, and an outgas sing prevention pattern sequentially stacked.
    Type: Application
    Filed: June 12, 2018
    Publication date: October 18, 2018
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sung-Hyun Choi, Yong-Suk Tak, Gi-Gwan Park, Bon-Young Koo, Ki-Yeon Park, Won-Oh Seo
  • Patent number: 10096688
    Abstract: An integrated circuit device includes a fin type active area protruding from a substrate and having an upper surface at a first level; a nanosheet extending in parallel to the upper surface of the fin type active area and comprising a channel area, the nanosheet being located at a second level spaced apart from the upper surface of the fin type active area; a gate disposed on the fin type active area and surrounding at least a part of the nanosheet, the gate extending in a direction crossing the fin type active area; a gate dielectric layer disposed between the nanosheet and the gate; a source and drain region formed on the fin type active area and connected to one end of the nanosheet; a first insulating spacer on the nanosheet, the first insulating spacer covering sidewalls of the gate; and a second insulating spacer disposed between the gate and the source and drain region in a space between the upper surface of the fin type active area and the nanosheet, the second insulating spacer having a multilayer st
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: October 9, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-suk Tak, Gi-gwan Park, Tae-jong Lee, Bon-young Koo, Ki-yeon Park, Sung-hyun Choi
  • Patent number: 10026736
    Abstract: A semiconductor device includes an active fin on a substrate, a gate structure on the active fin, a gate spacer structure on a sidewall of the gate structure, and a source/drain layer on at least a portion of the active fin adjacent the gate spacer structure. The gate spacer structure includes a wet etch stop pattern, an oxygen-containing silicon pattern, and an outgassing prevention pattern sequentially stacked.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: July 17, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Hyun Choi, Yong-Suk Tak, Gi-Gwan Park, Bon-Young Koo, Ki-Yeon Park, Won-Oh Seo
  • Patent number: 9972716
    Abstract: Provided are semiconductor devices that include an active pattern on a substrate, first and second gate electrodes on the active pattern and arranged in a first direction relative to one another and a first source/drain region in a first trench that extends into the active pattern between the first and second gate electrodes. The first source/drain region includes a first epitaxial layer that is configured to fill the first trench and that includes at least one plane defect that originates at a top portion of the first epitaxial layer and extends towards a bottom portion of the first epitaxial layer.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: May 15, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Bum Kim, Seok-Hoon Kim, Chul Kim, Kwan-Heum Lee, Byeong-Chan Lee, Cho-Eun Lee, Su-Jin Jung, Bon-Young Koo
  • Patent number: 9859393
    Abstract: A device includes: a gate line on an active region of a substrate, a pair of source/drain regions in the active region on both sides of the gate line, a contact plug on at least one source/drain region out of the pair of source/drain regions; and a multilayer-structured insulating spacer between the gate line and the contact plug. The multilayer-structured insulating spacer may include an oxide layer, a first carbon-containing insulating layer covering a first surface of the oxide layer adjacent to the gate line, and a second carbon-containing insulating layer covering a second surface of the oxide layer, opposite to the first surface of the oxide layer, adjacent to the contact plug.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: January 2, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong-suk Tak, Tae-jong Lee, Hyun-seung Kim, Bon-young Koo, Ki-yeon Park, Gi-gwan Park, Mi-seon Park
  • Patent number: 9859387
    Abstract: A semiconductor device includes a substrate having an upper surface, a plurality of active fins on the substrate, a gate electrode crossing the plurality of active fins, and at each side of the gate electrode, a source/drain region on the plurality of active fins. The source/drain region may include a plurality of first regions extending from the active fins, and a second region between each of the plurality of first regions. The second region may have a second germanium concentration greater than the first germanium concentration. The source/drain region may be connected to a contact plug, and may have a top surface that has a wave shaped, or curved surface. The top surface may have a larger surface area than a top surface of the contact plug.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: January 2, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin Bum Kim, Chul Sung Kim, Kang Hun Moon, Yang Xu, Bon Young Koo
  • Patent number: 9859376
    Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a multi-channel active pattern including germanium and an inner region and an outer region, the outer region formed along a profile of the inner region, and a germanium fraction of the outer region being smaller than a germanium fraction of the inner region. A gate electrode intersects the multi-channel active pattern.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: January 2, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han-ki Lee, Jae-Young Park, Dong-Hun Lee, Bon-Young Koo, Sun-Young Lee, Jae-Jong Han
  • Patent number: 9853111
    Abstract: A method of manufacturing a semiconductor device includes forming active fins on a substrate; forming source/drain regions on the active fins on both sides of a gate structure, the gate structure extending in a direction intersecting with a direction in which the active fins extend; forming an etch stop layer on the source/drain regions; forming an interlayer dielectric layer on the etch stop layer; forming a first opening by partially removing the interlayer dielectric layer so as not to expose the etch stop layer; forming an impurity region within the interlayer dielectric layer by implanting a first impurity ion through the first opening; forming a second opening by removing the impurity region so as to expose the etch stop layer; implanting a second impurity ion into the exposed etch stop layer; and removing the exposed etch stop layer.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: December 26, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung In Choi, Bon Young Koo, Hyun Gi Hong
  • Publication number: 20170317081
    Abstract: A semiconductor device includes a substrate, a first active fin and a second active fin on the substrate, respectively, a plurality of first epitaxial layers on the first active fin and on the second active fin, respectively, a plurality of second epitaxial layers on the plurality of first epitaxial layers, a bridge layer connecting the plurality of second epitaxial layers to each other, and a third epitaxial layer on the bridge layer.
    Type: Application
    Filed: July 19, 2017
    Publication date: November 2, 2017
    Inventors: SEOK-HOON KIM, JIN-BUM KIM, KWAN-HEUM LEE, BYEONG-CHAN LEE, CHO-EUN LEE, JIN-HEE HAN, BON-YOUNG KOO