Patents by Inventor Bong-Hyun Kim

Bong-Hyun Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8877634
    Abstract: The inventive concept provides methods of manufacturing semiconductor devices having a fine pattern. In some embodiments, the methods comprise forming an etch-target film on a substrate, forming a first mask pattern on the etch-target film, forming a second mask pattern by performing an ion implantation process in the first mask pattern, and etching the etch-target film using the second mask pattern.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: November 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Woon Shin, Bong-Hyun Kim, Su-Min Kim, Hyo-Jung Kim, Chang-Min Park, Soo-Jin Hong
  • Publication number: 20140264778
    Abstract: A precursor composition for forming a silicon dioxide film on a substrate, the precursor composition including at least one precursor compound represented by the following chemical formulas (1), (2), and (3): HxSiAy(NR1R2)4-x-y??(1) HxSi(NAR3)4-x??(2) HxSi(R4)z(R5)4-x-z??(3) wherein, independently in the chemical formulas (1), (2), and (3), H is hydrogen, x is 0 to 3, Si is silicon, A is a halogen, y is 1 to 4, N is nitrogen, and R1, R2, R3, and R5 are each independently selected from the group of H, aryl, perhaloaryl, C1-8 alkyl, and C1-8 perhaloalkyl, and R4 is aryl in which at least one hydrogen is replaced with a halogen or C1-8 alkyl in which at least one hydrogen is replaced with a halogen
    Type: Application
    Filed: February 14, 2014
    Publication date: September 18, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Han-Jin LIM, Bong-Hyun KIM, Seok-Woo NAM, Dong-Woon SHIN, In-Sang JEON, Soo-Jin HONG
  • Publication number: 20140167288
    Abstract: A semiconductor device includes a substrate having a conductive area, a first pattern formed on the substrate and having a contact hole through which the conductive area is exposed, and a contact plug in the contact hole. The contact plug includes first and second silicon layers. The first silicon layer, formed from a first compound including at least two silicon atoms, is formed in the contact hole to contact a top surface of the conductive area and a side wall of the first pattern. The second silicon layer, formed from a second compound including a number of silicon atoms less than the number of the silicon atoms of the first compound, is formed on the first silicon layer and fills a remaining space of the contact hole, the second silicon layer being spaced apart from the first pattern at an entrance of the contact hole.
    Type: Application
    Filed: February 21, 2014
    Publication date: June 19, 2014
    Inventors: Taek-soo Jeon, Bong-hyun Kim, Won-seok Yoo, Jae-hong Seo, Ho-kyun An, Dae-hyun Kim
  • Patent number: 8697570
    Abstract: A semiconductor device includes a substrate having a conductive area, a first pattern formed on the substrate and having a contact hole through which the conductive area is exposed, and a contact plug in the contact hole. The contact plug includes first and second silicon layers. The first silicon layer, formed from a first compound including at least two silicon atoms, is formed in the contact hole to contact a top surface of the conductive area and a side wall of the first pattern. The second silicon layer, formed from a second compound including a number of silicon atoms less than the number of the silicon atoms of the first compound, is formed on the first silicon layer and fills a remaining space of the contact hole, the second silicon layer being spaced apart from the first pattern at an entrance of the contact hole.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: April 15, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Taek-soo Jeon, Bong-hyun Kim, Won-seok Yoo, Jae-hong Seo, Ho-kyun An, Dae-hyun Kim
  • Publication number: 20130267092
    Abstract: The inventive concept provides methods of manufacturing semiconductor devices having a fine pattern. In some embodiments, the methods comprise forming an etch-target film on a substrate, forming a first mask pattern on the etch-target film, forming a second mask pattern by performing an ion implantation process in the first mask pattern, and etching the etch-target film using the second mask pattern.
    Type: Application
    Filed: December 19, 2012
    Publication date: October 10, 2013
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Dong-Woon Shin, Bong-Hyun Kim, Su-Min Kim, Hyo-Jung Kim, Chang-Min Park, Soo-Jin Hong
  • Publication number: 20120001267
    Abstract: An electrode structure is disclosed. The electrode structure includes a first polysilicon layer doped with resistance adjustment impurities; a second polysilicon layer for adjusting grains, formed in the first polysilicon layer and doped with grain adjustment impurities; an ohmic metal layer formed on the first and second polysilicon layers; a barrier metal layer formed on the ohmic metal layer; and a metal layer formed on the barrier metal layer.
    Type: Application
    Filed: June 27, 2011
    Publication date: January 5, 2012
    Inventors: Dong-kak Lee, Joon Kim, Bong-hyun Kim, Han-Jin Lim
  • Patent number: 8039344
    Abstract: In a method of forming a capacitor, a seed stopper and a sacrificial layer is formed on an insulating interlayer having a plug therethrough. An opening is formed through the sacrificial layer and the seed stopper to expose the plug. A seed is formed on an innerwall of the opening. A lower electrode is formed covering the seed on the innerwall of the opening. The sacrificial layer and the seed are removed. A dielectric layer and an upper electrode are sequentially formed on the lower electrode.
    Type: Grant
    Filed: November 24, 2010
    Date of Patent: October 18, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han-Jin Lim, Jae-Hong Seo, Seok-Woo Nam, Bong-Hyun Kim, Taek-Soo Jeon
  • Publication number: 20110222207
    Abstract: In a method of forming a dielectric layer structure, a precursor thin film chemisorbed on a substrate in a process chamber is formed using a source gas including a metal precursor. The process chamber is purged and pumped out to remove a remaining source gas therein and to remove any metal precursor physisorbed on the precursor thin film. The forming of the precursor thin film and the purging and pumping out of the process chamber are alternately and repeatedly performed to form a multi-layer precursor thin film. An oxidant is provided onto the multilayer precursor thin film to form a bulk oxide layer.
    Type: Application
    Filed: March 14, 2011
    Publication date: September 15, 2011
    Inventors: Tae-Jong Lee, Jae-Young Park, Jong-Bom Seo, Seok-Woo Nam, Bong-Hyun Kim, Han-Jin Lim, Seung-Sik Chung
  • Patent number: 8012823
    Abstract: Provided are methods of fabricating capacitors of semiconductor devices, the methods including: forming a lower electrode on a semiconductor substrate, performing a pre-process operation on the lower electrode for suppressing deterioration of the lower electrode during a process, forming a dielectric layer on the lower electrode using a source gas and an ozone gas, and forming an upper electrode on the dielectric layer, wherein the pre-process operation and the forming of the dielectric layer may be performed in one device capable of atomic layer deposition.
    Type: Grant
    Filed: May 15, 2009
    Date of Patent: September 6, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han-jin Lim, Jae-young Park, Young-jin Kim, Seok-woo Nam, Bong-hyun Kim, Kyoung-ryul Yoon, Jae-hyoung Choi, Beom-jong Kim
  • Publication number: 20110198758
    Abstract: A semiconductor device includes a substrate having a conductive area, a first pattern formed on the substrate and having a contact hole through which the conductive area is exposed, and a contact plug in the contact hole. The contact plug includes first and second silicon layers. The first silicon layer, formed from a first compound including at least two silicon atoms, is formed in the contact hole to contact a top surface of the conductive area and a side wall of the first pattern. The second silicon layer, formed from a second compound including a number of silicon atoms less than the number of the silicon atoms of the first compound, is formed on the first silicon layer and fills a remaining space of the contact hole, the second silicon layer being spaced apart from the first pattern at an entrance of the contact hole.
    Type: Application
    Filed: November 8, 2010
    Publication date: August 18, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Taek-soo Jeon, Bong-hyun Kim, Won-seok Yoo, Jae-hong Seo, Ho-kyun An, Dae-hyun Kim
  • Publication number: 20110124176
    Abstract: In a method of forming a capacitor, a seed stopper and a sacrificial layer is formed on an insulating interlayer having a plug therethrough. An opening is formed through the sacrificial layer and the seed stopper to expose the plug. A seed is formed on an innerwall of the opening. A lower electrode is formed covering the seed on the innerwall of the opening. The sacrificial layer and the seed are removed. A dielectric layer and an upper electrode are sequentially formed on the lower electrode.
    Type: Application
    Filed: November 24, 2010
    Publication date: May 26, 2011
    Inventors: Han-Jin Lim, Jae-Hong Seo, Seok-Woo Nam, Bong-Hyun Kim, Taek-Soo Jeon
  • Publication number: 20100009508
    Abstract: Provided are methods of fabricating capacitors of semiconductor devices, the methods including: forming a lower electrode on a semiconductor substrate, performing a pre-process operation on the lower electrode for suppressing deterioration of the lower electrode during a process, forming a dielectric layer on the lower electrode using a source gas and an ozone gas, and forming an upper electrode on the dielectric layer, wherein the pre-process operation and the forming of the dielectric layer may be performed in one device capable of atomic layer deposition.
    Type: Application
    Filed: May 15, 2009
    Publication date: January 14, 2010
    Inventors: Han-jin Lim, Jae-young Park, Young-jin Kim, Seok-woo Nam, Bong-hyun Kim, Kyoung-ryul Yoon, Jae-hyoung Chol, Beom-jong Kim
  • Patent number: 7592227
    Abstract: Example embodiments of the present invention relate to methods of manufacturing a semiconductor device. Other example embodiments of the present invention relate to methods of manufacturing a semiconductor device having a gate electrode. In the method of manufacturing the semiconductor device, a gate electrode may be formed on a semiconductor substrate. Damage in the semiconductor substrate and a sidewall of the gate electrode may be cured, or repaired, by a radical re-oxidation process to form an oxide layer on the semiconductor substrate and the gate electrode.
    Type: Grant
    Filed: July 7, 2006
    Date of Patent: September 22, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Sun Lee, Jai-Dong Lee, Bong-Hyun Kim, Man-Sug Kang, Jung-Hwan Kim, Hyun-Jin Shin, Won-Seok Yoo, Seung-Mok Shin
  • Patent number: 7521375
    Abstract: In methods of forming an oxide layer and an oxynitride layer, a substrate is loaded into a reaction chamber having a first pressure and a first temperature. The oxide layer is formed on the substrate using a reaction gas while increasing a temperature of the reaction chamber from the first temperature to a second temperature under a second pressure. Additionally, the oxide layer is nitrified in the reaction chamber to form the oxynitride layer on the substrate. When the oxide layer and/or the oxynitride layer are formed on the substrate, minute patterns of a semiconductor device, for example a DRAM device, an SRAM device or an LOGIC device may be easily formed on the oxide layer or the oxynitride layer.
    Type: Grant
    Filed: October 5, 2007
    Date of Patent: April 21, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-sub You, Hun-Hyeoung Leam, Seok-Woo Nam, Bong-Hyun Kim, Woong Lee, Sang-Hoon Lee
  • Patent number: 7506981
    Abstract: The present invention is related to an image acquisition/output apparatus and a picture system for ophthalmic operation using the same. The picture system for ophthalmic operation according to the present invention includes a near-infrared microscope for irradiating an affect part through an objective lens with near-infrared ray emitted from a light source, and transmitting near-infrared images formed by the objective lens to a first and a second ocular lenses, an image acquisition apparatus for converting near-infrared images transmitted to the first and the second ocular lenses into a first and a second electrical image signals for output, and a display apparatus for receiving the first and the second image signals and outputting them in three-dimensional images.
    Type: Grant
    Filed: February 28, 2005
    Date of Patent: March 24, 2009
    Inventor: Bong-Hyun Kim
  • Publication number: 20080268653
    Abstract: A method of forming a high dielectric film using atomic layer deposition (ALD), and a method of manufacturing a capacitor having the high dielectric film, include supplying a precursor containing a metal element to a semiconductor substrate and purging a reactor; supplying an oxidizer and purging the reactor; and supplying a reaction source containing nitrogen and purging the reactor.
    Type: Application
    Filed: June 5, 2008
    Publication date: October 30, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyoung-seok KIM, Hong-bae PARK, Bong-hyun KIM, Sung-tae KIM, Jong-wan KWON, Jung-hyun LEE, Ki-chul KIM, Jae-soon LIM, Gab-jin NAM, Young-sun KIM
  • Patent number: 7396719
    Abstract: A method of forming a high dielectric film using atomic layer deposition (ALD), and a method of manufacturing a capacitor having the high dielectric film, include supplying a precursor containing a metal element to a semiconductor substrate and purging a reactor; supplying an oxidizer and purging the reactor; and supplying a reaction source containing nitrogen and purging the reactor.
    Type: Grant
    Filed: June 23, 2004
    Date of Patent: July 8, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung-seok Kim, Hong-bae Park, Bong-hyun Kim, Sung-tae Kim, Jong-wan Kwon, Jung-hyun Lee, Ki-chul Kim, Jae-soon Lim, Gab-jin Nam, Young-sun Kim
  • Publication number: 20080090424
    Abstract: In methods of forming an oxide layer and an oxynitride layer, a substrate is loaded into a reaction chamber having a first pressure and a first temperature. The oxide layer is formed on the substrate using a reaction gas while increasing a temperature of the reaction chamber from the first temperature to a second temperature under a second pressure. Additionally, the oxide layer is nitrified in the reaction chamber to form the oxynitride layer on the substrate. When the oxide layer and/or the oxynitride layer are formed on the substrate, minute patterns of a semiconductor device, for example a DRAM device, an SRAM device or an LOGIC device may be easily formed on the oxide layer or the oxynitride layer.
    Type: Application
    Filed: October 5, 2007
    Publication date: April 17, 2008
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Young-Sub You, Hun-Hyeoung Leam, Seok-Woo Nam, Bong-Hyun Kim, Woong Lee, Sang-Hoon Lee
  • Patent number: 7297620
    Abstract: In methods of forming an oxide layer and an oxynitride layer, a substrate is loaded into a reaction chamber having a first pressure and a first temperature. The oxide layer is formed on the substrate using a reaction gas while increasing a temperature of the reaction chamber from the first temperature to a second temperature under a second pressure. Additionally, the oxide layer is nitrified in the reaction chamber to form the oxynitride layer on the substrate. When the oxide layer and/or the oxynitride layer are formed on the substrate, minute patterns of a semiconductor device, for example a DRAM device, an SRAM device or an LOGIC device may be easily formed on the oxide layer or the oxynitride layer.
    Type: Grant
    Filed: May 6, 2004
    Date of Patent: November 20, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Sub You, Hun-Hyeoung Leam, Seok-Woo Nam, Bong-Hyun Kim, Woong Lee, Sang-Hoon Lee
  • Publication number: 20070085207
    Abstract: A pad structure, a method of forming a pad structure, a semiconductor device having a pad structure and a method of manufacturing a semiconductor device are disclosed. The pad structure may include a first pad, a second pad, a third pad and/or a spacer. The first pad may contact a contact region on a substrate. The first pad may include doped polysilicon. The second pad may contact the first pad. The second pad may include a metal silicide or a metal silicongermanium. The third pad may contact the second pad. The third pad may include a conductive material (e.g., doped polysilicon, a metal or a metal nitride). The spacer may be formed on sidewalls of the second and the third pads.
    Type: Application
    Filed: August 2, 2006
    Publication date: April 19, 2007
    Inventors: Woo-Sung Lee, Young-Wook Park, Nam-Kyu Kim, Bong-Hyun Kim, Man-Sug Kang