Abstract: A host device interfacing with a point of deployment (POD) and method of processing broadcasting data are disclosed. An IP physical interface unit receives a frame including an internet protocol (IP) packet carrying broadcast data through a network modem. A routing engine routs the frame based on a destination information included in the frame. An IP to TS Decapsulator extracts a MPEG-2 TS packet from the IP packet included in the routed frame. And a multiplexer augments the extracted MPEG-2 TS packet with Packet Header carrying an identification information, multiplexes the augmented MPEG-2 TS packet and forwards the multiplexed MPEG-2 TS to the POD.

Abstract: A host includes a controller configured to receive a request external to the host, wherein the request is for diagnostic information associated with central processing unit (CPU) for an application. The controller is further configured to collect the requested diagnostic information.

Abstract: An apparatus and method for processing channel information in a broadcasting system for transmitting/receiving a cable broadcasting signal are disclosed. In particular, a headend which transmits a broadcasting signal and channel information transmits plural pieces of channel information having different sizes with respect to a single channel to broadcasting receivers. Each of the broadcasting receivers selects most suitable channel information from the plural pieces of channel information of the single channel and displays the selected channel information on a screen for the channel. Accordingly, it is possible to provide users with the channel information which can most accurately represent the contents of the displayed channel.

Abstract: A memory merged logic (MML) semiconductor device of NMOS and PMOS dual gate structure including embedded memory of a self-aligned structure and a method of manufacturing the same, wherein in the MML semiconductor device, the memory area including n-type metal oxide semiconductor (NMOS) and p-type metal oxide semiconductor (PMOS) are integrated together, wherein the memory area includes a polycide gate electrode, a hard mask pattern comprised of nitride materials which is formed on the polycide gate electrode, a spacer comprised of nitride materials formed along the sidewall of the polycide gate electrode, and a self-aligned contact which is formed between the adjacent spacers and electrically connected with an impurity implantation region formed on a semiconductor substrate. The logic area includes salicided NMOS and PMOS gate electrodes and salicided source/drain regions, and the height of the polycide gate electrode is smaller than the height of the NMOS and PMOS gate electrodes.

Abstract: A memory merged logic (MML) semiconductor device of NMOS and PMOS dual gate structure including embedded memory of a self-aligned structure and a method of manufacturing the same, wherein in the MML semiconductor device, the memory area including n-type metal oxide semiconductor (NMOS) and p-type metal oxide semiconductor (PMOS) are integrated together, wherein the memory area includes a polycide gate electrode, a hard mask pattern comprised of nitride materials which is formed on the polycide gate electrode, a spacer comprised of nitride materials formed along the sidewall of the polycide gate electrode, and a self-aligned contact which is formed between the adjacent spacers and electrically connected with an impurity implantation region formed on a semiconductor substrate. The logic area includes salicided NMOS and PMOS gate electrodes and salicided source/drain regions, and the height of the polycide gate electrode is smaller than the height of the NMOS and PMOS gate electrodes.

Abstract: A memory merged logic (MML) semiconductor device of NMOS and PMOS dual gate structure including embedded memory of a self-aligned structure and a method of manufacturing the same, wherein in the MML semiconductor device, the memory area including n-type metal oxide semiconductor (NMOS) and p-type metal oxide semiconductor (PMOS) are integrated together, wherein the memory area includes a polycide gate electrode, a hard mask pattern comprised of nitride materials which is formed on the polycide gate electrode, a spacer comprised of nitride materials formed along the sidewall of the polycide gate electrode, and a self-aligned contact which is formed between the adjacent spacers and electrically connected with an impurity implantation region formed on a semiconductor substrate. The logic area includes salicided NMOS and PMOS gate electrodes and salicided source/drain regions, and the height of the polycide gate electrode is smaller than the height of the NMOS and PMOS gate electrodes.

Abstract: A surveillance system and method are disclosed. Two images that occur at a certain time apart are captured. The luminance of each pixel for each image is determined. The change in luminance for each pixel is determined. The number of pixels whose change in luminance exceeds a first threshold is calculated. If this number of pixels exceeding a first threshold exceeds a second threshold, the image is stored as the image has sufficiently changed. Since the present image is stored when there is a movement in the present image compared with the previous image, the cost for storing image data is low. Further, when there is a movement, since the time intervals for capturing images are adjusted according to the extent of the movement, the surveillance operation can be carried out effectively.

Abstract: A memory merged logic (MML) semiconductor device of NMOS and PMOS dual gate structure including embedded memory of a self-aligned structure and a method of manufacturing the same, wherein in the MML semiconductor device, the memory area including n-type metal oxide semiconductor (NMOS) and p-type metal oxide semiconductor (PMOS) are integrated together, wherein the memory area includes a polycide gate electrode, a hard mask pattern comprised of nitride materials which is formed on the polycide gate electrode, a spacer comprised of nitride materials formed along the sidewall of the polycide gate electrode, and a self-aligned contact which is formed between the adjacent spacers and electrically connected with an impurity implantation region formed on a semiconductor substrate. The logic area includes salicided NMOS and PMOS gate electrodes and salicided source/drain regions, and the height of the polycide gate electrode is smaller than the height of the NMOS and PMOS gate electrodes.

Abstract: A monitor with an integrally formed storage rack can hold a variety of recording media, will be economical to produce, will not increase the amount of desk space required by the monitor, will reduce clutter at computer work station, and will reduce the amount of misplaced or lost recording media. If a user wants to store recording media having a different thickness or wishes to have a precise fit for existing recording media, then the two plates can simply be exchanged for plates having bars spaced along the bars at an appropriate interval.