Abstract: A method for simulation of lithography overlay is disclosed which comprises storing alignment parameters used to align a semiconductor wafer prior to a lithography step; storing process control parameters used during the lithography step on the semiconductor wafer, storing overlay parameters measured after the lithography step, calculating alternative alignment parameters and alternative process control parameters. The alternative alignment parameters and the alternative process control parameters are added to cleansed overlay parameters to obtain simulated lithography overlay data.

Abstract: A method of calculating an overlay correction model in a unit for the fabrication of a wafer is disclosed. The method comprises measuring overlay deviations of a subset of first overlay marks and second overlay marks by determining the differences between the subset of first overlay marks generated in the first layer and corresponding ones of the subset of second overlay marks generated in the second layer.

Abstract: Photoresist layers are exposed to an exposure beam by using an exposure tool assembly, wherein the photoresist layers coat semiconductor substrates and wherein for each exposure a current exposure parameter set is used that includes at least a defocus value and an exposure dose. The exposed photoresist layers are developed, wherein resist patterns are formed from the photoresist layers. Feature characteristics in the resist patterns and/or in substrate patterns derived from the resist patterns are measured. The current exposure parameter set is updated in response to deviations of the measured feature characteristics from target feature characteristics. De-corrected feature characteristics of hypothetical resist patterns are estimated, which would be formed without updating the exposure parameter set. In response to information obtained from the de-corrected feature characteristics the measurement strategy for the feature characteristics may be changed or the current exposure parameter set may be updated.

Abstract: An apparatus and a method for analysis of processing of a semiconductor wafer is disclosed which comprises gathering a plurality of items of processing data, applying at least one process model to the at least some of the plurality of items of processing data to derive at least one set of process results, comparing at least some of the derived sets of process results or at least some of the plurality of items of processing data with a process window, and outputting a set of comparison results based on the comparison of the derived sets of process results or the plurality of items of processing data with the process window.

Abstract: A method for simulation of lithography overlay is disclosed which comprises storing alignment parameters used to align a semiconductor wafer prior to a lithography step; storing process control parameters used during the lithography step on the semiconductor wafer, storing overlay parameters measured after the lithography step, calculating alternative alignment parameters and alternative process control parameters. The alternative alignment parameters and the alternative process control parameters are added to cleansed overlay parameters to obtain simulated lithography overlay data.

Abstract: Photoresist layers are exposed to an exposure beam by using an exposure tool assembly, wherein the photoresist layers coat semiconductor substrates and wherein for each exposure a current exposure parameter set is used that includes at least a defocus value and an exposure dose. The exposed photoresist layers are developed, wherein resist patterns are formed from the photoresist layers. Feature characteristics in the resist patterns and/or in substrate patterns derived from the resist patterns are measured. The current exposure parameter set is updated in response to deviations of the measured feature characteristics from target feature characteristics. De-corrected feature characteristics of hypothetical resist patterns are estimated, which would be formed without updating the exposure parameter set. In response to information obtained from the de-corrected feature characteristics the measurement strategy for the feature characteristics may be changed or the current exposure parameter set may be updated.

Abstract: A method for simulation of lithography overlay is disclosed which comprises storing alignment parameters used to align a semiconductor wafer prior to a lithography step; storing process control parameters used during the lithography step on the semiconductor wafer; storing overlay parameters measured after the lithography step; calculating alternative alignment parameters and alternative process control parameters. The alternative alignment parameters and the alternative process control parameters are added to cleansed overlay parameters to obtain simulated lithography overlay data.

Abstract: A method of calculating an overlay correction model in a unit for the fabrication of a wafer is disclosed. The method comprises measuring overlay deviations of a subset of first overlay marks and second overlay marks by determining the differences between the subset of first overlay marks generated in the first layer and corresponding ones of the subset of second overlay marks generated in the second layer.

Abstract: A method and apparatus for evaluating and controlling a semiconductor manufacturing process having a plurality of process steps in a process flow is described. The method comprises retrieving measurements of process step parameters from a process measurement database. The process step parameters comprise at least one of process step measurement data, process step context data or process step control data. The process step parameters are subsequently associated with one or more of the process steps.

Abstract: A method of calculating an overlay correction model in a unit for the fabrication of a wafer is disclosed. The method comprises measuring overlay deviations of a subset of first overlay marks and second overlay marks by determining the differences between the subset of first overlay marks generated in the first layer and corresponding ones of the subset of second overlay marks generated in the second layer.

Abstract: A method of manufacturing semiconductor devices includes defining a sampling plan that contains position information about metrology sites on process wafers. A first property of the process wafers is measured to obtain measurement values at measurement points, wherein a quantity of the measurement points per process wafer is at least tenfold a quantity of the metrology sites. A sampling model that includes at least a wafer model is updated on the basis of the measurement values. The sampling plan is updated on the basis of an assessment of deviations of the measurement values from a current sampling model.

Abstract: An apparatus and a method for analysis of processing of a semiconductor wafer is disclosed which comprises gathering a plurality of items of processing data, applying at least one process model to the at least some of the plurality of items of processing data to derive at least one set of process results, comparing at least some of the derived sets of process results or at least some of the plurality of items of processing data with a process window, and outputting a set of comparison results based on the comparison of the derived sets of process results or the plurality of items of processing data with the process window.

Abstract: An apparatus and a method for analysis of processing of a semiconductor wafer is disclosed which comprises gathering a plurality of items of processing data, applying at least one process model to the at least some of the plurality of items of processing data to derive at least one set of process results, comparing at least some of the derived sets of process results or at least some of the plurality of items of processing data with a process window, and outputting a set of comparison results based on the comparison of the derived sets of process results or the plurality of items of processing data with the process window.

Abstract: A method of manufacturing semiconductor devices includes defining a sampling plan that contains position information about metrology sites on process wafers. A first property of the process wafers is measured to obtain measurement values at measurement points, wherein a quantity of the measurement points per process wafer is at least tenfold a quantity of the metrology sites. A sampling model that includes at least a wafer model is updated on the basis of the measurement values. The sampling plan is updated on the basis of an assessment of deviations of the measurement values from a current sampling model.

Abstract: A method and apparatus for evaluating and controlling a semiconductor manufacturing process having a plurality of process steps in a process flow is described. The method comprises retrieving measurements of process step parameters from a process measurement database. The process step parameters comprise at least one of process step measurement data, process step context data or process step control data. The process step parameters are subsequently associated with one or more of the process steps.

Abstract: A method of calculating an overlay correction model in a unit for the fabrication of a wafer is disclosed. The method comprises measuring overlay deviations of a subset of first overlay marks and second overlay marks by determining the differences between the subset of first overlay marks generated in the first layer and corresponding ones of the subset of second overlay marks generated in the second layer.

Abstract: An apparatus and a method for analysis of processing of a semiconductor wafer is disclosed which comprises gathering a plurality of items of processing data, applying at least one process model to the at least some of the plurality of items of processing data to derive at least one set of process results, comparing at least some of the derived sets of process results or at least some of the plurality of items of processing data with a process window, and outputting a set of comparison results based on the comparison of the derived sets of process results or the plurality of items of processing data with the process window.

Abstract: A method of calculating an overlay correction model in a unit for the fabrication of a wafer is disclosed. The method comprises measuring overlay deviations of a subset of first overlay marks and second overlay marks by determining the differences between the subset of first overlay marks generated in the first layer and corresponding ones of the subset of second overlay marks generated in the second layer.

Abstract: A method for simulation of lithography overlay is disclosed which comprises storing alignment parameters used to align a semiconductor wafer prior to a lithography step; storing process control parameters used during the lithography step on the semiconductor wafer; storing overlay parameters measured after the lithography step; calculating alternative alignment parameters and alternative process control parameters. The alternative alignment parameters and the alternative process control parameters are added to cleansed overlay parameters to obtain simulated lithography overlay data.

Abstract: A method of calculating an overlay correction model in a unit for the fabrication of a wafer is disclosed. The method comprises measuring overlay deviations of a subset of first overlay marks and second overlay marks by determining the differences between the subset of first overlay marks generated in the first layer and corresponding ones of the subset of second overlay marks generated in the second layer.