Patents by Inventor Boris Peres
Boris Peres has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8729565Abstract: A FET includes a first and second set of finger arrays that each include a source, gate and drain. A first source pad is electrically coupled to source electrodes in the first set of finger arrays. A second source pad is electrically coupled to the source electrodes in the second set of finger arrays. A common drain pad is electrically coupled to drain electrodes in the first and second set of finger arrays. A first gate pad is electrically coupled to gate electrodes in the first set of finger arrays. A second gate pad is electrically coupled to gate electrodes in the second set of finger arrays. A substrate is also provided on which are disposed the first and second set of finger arrays, the first and second source pads, the common drain pad, and the first and second gate pads.Type: GrantFiled: August 13, 2013Date of Patent: May 20, 2014Assignee: Power Integrations, Inc.Inventors: LinLin Liu, Milan Pophristic, Boris Peres
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Publication number: 20130328060Abstract: A FET includes a first and second set of finger arrays that each include a source, gate and drain. A first source pad is electrically coupled to source electrodes in the first set of finger arrays. A second source pad is electrically coupled to the source electrodes in the second set of finger arrays. A common drain pad is electrically coupled to drain electrodes in the first and second set of finger arrays. A first gate pad is electrically coupled to gate electrodes in the first set of finger arrays. A second gate pad is electrically coupled to gate electrodes in the second set of finger arrays. A substrate is also provided on which are disposed the first and second set of finger arrays, the first and second source pads, the common drain pad, and the first and second gate pads.Type: ApplicationFiled: August 13, 2013Publication date: December 12, 2013Applicant: POWER INTEGRATIONS, INC.Inventors: LinLin Liu, Milan Pophristic, Boris Peres
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Patent number: 8530903Abstract: A FET includes a first and second set of finger arrays that each include a source, gate and drain. A first source pad is electrically coupled to source electrodes in the first set of finger arrays. A second source pad is electrically coupled to the source electrodes in the second set of finger arrays. A common drain pad is electrically coupled to drain electrodes in the first and second set of finger arrays. A first gate pad is electrically coupled to gate electrodes in the first set of finger arrays. A second gate pad is electrically coupled to gate electrodes in the second set of finger arrays. A substrate is also provided on which are disposed the first and second set of finger arrays, the first and second source pads, the common drain pad, and the first and second gate pads.Type: GrantFiled: October 19, 2012Date of Patent: September 10, 2013Assignee: Power Integrations, Inc.Inventors: LinLin Liu, Milan Pophristic, Boris Peres
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Patent number: 8319256Abstract: A FET includes a substrate, a buffer layer disposed on the substrate, a channel layer disposed over the buffer layer and a barrier layer disposed over the channel layer. Source, gate and drain electrodes are located over the barrier layer and extend in a longitudinal direction thereon. A portion of the channel and barrier layers define a mesa extending in the longitudinal direction and the source and drain electrodes extend beyond an edge of the mesa. The gate electrodes extend along an edge sidewall of the mesa. A conductive source interconnect is disposed over the buffer layer and have a first end electrically connected to the source electrode. A first dielectric layer is disposed over the buffer layer and over the source interconnect. A gate via is formed in the first dielectric layer. A conductive gate node extends along the buffer layer and electrically connects the portion of the gate electrode extending along the sidewall of the mesa.Type: GrantFiled: June 23, 2010Date of Patent: November 27, 2012Assignee: Power Integrations, Inc.Inventors: Linlin Liu, Milan Pophristic, Boris Peres
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Publication number: 20110316045Abstract: A FET includes a substrate, a buffer layer disposed on the substrate, a channel layer disposed over the buffer layer and a barrier layer disposed over the channel layer. Source, gate and drain electrodes are located over the barrier layer and extend in a longitudinal direction thereon. A portion of the channel and barrier layers define a mesa extending in the longitudinal direction and the source and drain electrodes extend beyond an edge of the mesa. The gate electrodes extend along an edge sidewall of the mesa. A conductive source interconnect is disposed over the buffer layer and have a first end electrically connected to the source electrode. A first dielectric layer is disposed over the buffer layer and over the source interconnect. A gate via is formed in the first dielectric layer. A conductive gate node extends along the buffer layer and electrically connects the portion of the gate electrode extending along the sidewall of the mesa.Type: ApplicationFiled: June 23, 2010Publication date: December 29, 2011Applicant: VELOX SEMICONDUCTOR CORPORATIONInventors: Linlin LIU, Milan POPHRISTIC, Boris Peres
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Publication number: 20100140627Abstract: A packaged semiconductor device including a semiconductor die mounted on a header of a leadframe. A plurality of spaced external conductors extends from the header and at least one of the external conductors has a bond wire post at one end thereof such that a bonding wire extends between the bond wire post and the semiconductor die. The package device also includes a housing, which encloses the semiconductor die, the header, the bonding wire and the bonding wire post resulting in an insulated packaged device.Type: ApplicationFiled: October 8, 2009Publication date: June 10, 2010Inventors: Bryan S. Shelton, Marek K. Pabisz, TingGang Zhu, Linlin Liu, Boris Peres
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Patent number: 7115896Abstract: A nitride semiconductor is grown on a silicon substrate by depositing a few mono-layers of aluminum to protect the silicon substrate from ammonia used during the growth process, and then forming a nucleation layer from aluminum nitride and a buffer structure including multiple superlattices of AlRGa(1-R)N semiconductors having different compositions and an intermediate layer of GaN or other Ga-rich nitride semiconductor. The resulting structure has superior crystal quality. The silicon substrate used in epitaxial growth is removed before completion of the device so as to provide superior electrical properties in devices such as high-electron mobility transistors.Type: GrantFiled: November 25, 2003Date of Patent: October 3, 2006Assignee: Emcore CorporationInventors: Shiping Guo, David Gotthold, Milan Pophristic, Boris Peres, Ivan Eliashevich, Bryan S. Shelton, Alex D. Ceruzzi, Michael Murphy, Richard A. Stall
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Patent number: 7116567Abstract: A converter is provided having an AC input and a DC output. The converter includes a rectifier that receives the AC input and that provides a rectifier output, a series connected current to magnetic field energy storage device and current interrupter connected across the rectifier output and a series connected gallium nitride diode and output charge storage device connected between a midpoint of the series connected magnetic field energy storage device and current interrupter and a terminal of the rectifier output and wherein the converter is characterized in not needing a transient voltage suppression circuit.Type: GrantFiled: January 5, 2005Date of Patent: October 3, 2006Assignee: Velox Semiconductor CorporationInventors: Bryan S. Shelton, Boris Peres, Daniel McGlynn
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Patent number: 7084475Abstract: A lateral conduction Schottky diode includes multiple mesa regions upon which Schottky contacts are formed and which are at least separated by ohmic contacts to reduce the current path length and reduce current crowding in the Schottky contact, thereby reducing the forward resistance of a device. The multiple mesas may be isolated from one another and have sizes and shapes optimized for reducing the forward resistance. Alternatively, some of the mesas may be finger-shaped and intersect with a central mesa or a bridge mesa, and some or all of the ohmic contacts are interdigitated with the finger-shaped mesas. The dimensions of the finger-shaped mesas and the perimeter of the intersecting structure may be optimized to reduce the forward resistance. The Schottky diodes may be mounted to a submount in a flip chip arrangement that further reduces the forward voltage as well as improves power dissertation and reduces heat generation.Type: GrantFiled: February 17, 2004Date of Patent: August 1, 2006Assignee: Velox Semiconductor CorporationInventors: Bryan S. Shelton, Linlin Liu, Alex D. Ceruzzi, Michael Murphy, Milan Pophristic, Boris Peres, Richard A. Stall, Xiang Gao, Ivan Eliashevich
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Publication number: 20060154455Abstract: A nitride semiconductor is grown on a silicon substrate by depositing a few mono-layers of aluminum to protect the silicon substrate from ammonia used during the growth process, and then forming a nucleation layer from aluminum nitride and a buffer structure including multiple superlattices of AlRGa(1-R)N semiconductors having different compositions and an intermediate layer of GaN or other Ga-rich nitride semiconductor. The resulting structure has superior crystal quality. The silicon substrate used in epitaxial growth is removed before completion of the device so as to provide superior electrical properties in devices such as high-electron mobility transistors.Type: ApplicationFiled: March 9, 2006Publication date: July 13, 2006Applicant: Emcore CorporationInventors: Shiping Guo, David Gotthold, Milan Pophristic, Boris Peres, Ivan Eliashevich, Bryan Shelton, Alex Ceruzzi, Michael Murphy, Richard Stall
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Publication number: 20060151868Abstract: A packaged semiconductor device, in particular a gallium nitride semiconductor structure including a lower semiconductor layer and an upper semiconductor layer disposed over a portion of the lower semiconductor layer. The semiconductor structure includes a plurality of mesas projecting upwardly from the lower layer, each of the mesas including a portion of the upper layer and defining an upper contact surface separated form adjacent mesas by a portion of the lower layer surface. The device further includes a die mounting support, wherein the bottom surface of the die is attached to the top surface of the die mounting support; and a plurality of spaced external conductors extending from the support, at least once of said spaced external conductors having a bond wire post at one end thereof; with a bonding wire extending between the bond wire post and a contact region to the top surface of the plurality of mesas.Type: ApplicationFiled: January 10, 2005Publication date: July 13, 2006Inventors: TingGang Zhu, Bryan Shelton, Marek Pabisz, Mark Gottfried, Linlin Liu, Boris Peres, Alex Ceruzzi
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Publication number: 20060145674Abstract: A converter is provided having an AC input and a DC output. The converter includes a rectifier that receives the AC input and that provides a rectifier output, a series connected current to magnetic field energy storage device and current interrupter connected across the rectifier output and a series connected gallium nitride diode and output charge storage device connected between a midpoint of the series connected magnetic field energy storage device and current interrupter and a terminal of the rectifier output and wherein the converter is characterized in not needing a transient voltage suppression circuit.Type: ApplicationFiled: January 5, 2005Publication date: July 6, 2006Applicant: Emcore CorporationInventors: Bryan Shelton, Boris Peres, Daniel McGlynn
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Publication number: 20050179104Abstract: A lateral conduction Schottky diode includes multiple mesa regions upon which Schottky contacts are formed and which are at least separated by ohmic contacts to reduce the current path length and reduce current crowding in the Schottky contact, thereby reducing the forward resistance of a device. The multiple mesas may be isolated from one another and have sizes and shapes optimized for reducing the forward resistance. Alternatively, some of the mesas may be finger-shaped and intersect with a central mesa or a bridge mesa, and some or all of the ohmic contacts are interdigitated with the finger-shaped mesas. The dimensions of the finger-shaped mesas and the perimeter of the intersecting structure may be optimized to reduce the forward resistance. The Schottky diodes may be mounted to a submount in a flip chip arrangement that further reduces the forward voltage as well as improves power dissertation and reduces heat generation.Type: ApplicationFiled: February 17, 2004Publication date: August 18, 2005Applicant: Emcore CorporationInventors: Bryan Shelton, Linlin Liu, Alex Ceruzzi, Michael Murphy, Milan Pophristic, Boris Peres, Richard Stall, Xiang Gao, Ivan Eliashevich
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Publication number: 20040119063Abstract: A nitride semiconductor is grown on a silicon substrate by depositing a few mono-layers of aluminum to protect the silicon substrate from ammonia used during the growth process, and then forming a nucleation layer from aluminum nitride and a buffer structure including multiple superlattices of AlRGa(1−R)N semiconductors having different compositions and an intermediate layer of GaN or other Ga-rich nitride semiconductor. The resulting structure has superior crystal quality. The silicon substrate used in epitaxial growth is removed before completion of the device so as to provide superior electrical properties in devices such as high-electron mobility transistors.Type: ApplicationFiled: November 25, 2003Publication date: June 24, 2004Applicant: Emcore CorporationInventors: Shiping Guo, David Gotthold, Milan Pophristic, Boris Peres, Ivan Eliashevich, Bryan S. Shelton, Alex D. Ceruzzi, Michael Murphy, Richard A. Stall