Abstract: Provided are a display panel and an electronic device, and the display panel includes: shift registers, pressure detecting units and switching circuits; the switching circuit includes a first switching transistor and a second switching transistor, and a control terminal of the first switching transistor is electrically connected with an outputting terminal of one of the shift registers and an inputting terminal of the first switching transistor is electrically connected to a first outputting terminal of the corresponding pressure detecting unit, and a control terminal of the second switching transistor is electrically connected to an outputting terminal of one of the shift registers and an inputting terminal of the second switching transistor is electrically connected to a second outputting terminal of corresponding pressure detecting unit.

Abstract: A display panel and a display device are disclosed. The display panel includes at least one notch which includes a protrusion structure. A non-display region includes at least one first non-display region arranged along edges of the protrusion structure. At least one first pressure sensor is provided in the first non-display region. An included angle between a first strain detection direction of the first pressure sensor and a first edge of the display panel is greater than or equal to 65 degrees and less than or equal to 115 degrees. An included angle between a second strain detection direction and the first edge of the display panel is greater than or equal to ?25 degrees and less than or equal to 0 degree. A control chip is provided in the non-display region, and the first edge is an edge of the display panel close to the control chip.

Abstract: A liquid crystal display panel and a liquid crystal display device are provided. The liquid crystal display panel comprises a first substrate, a second substrate, a liquid crystal layer sandwiched between the first and second substrate, and an auxiliary electrode. The first substrate includes a plurality of gate electrode lines and a plurality of data lines intersected to define a plurality of pixel units. Each pixel unit corresponds to a pixel electrode and a common electrode. In each region corresponding to one pixel unit, the pixel electrode and the common electrode are configured to form an electric field that drives the liquid crystal layer. A vertical projection of the auxiliary electrode on the first substrate covers an area where the electric field is formed by the pixel electrode and the common electrode, and a thickness of the liquid crystal layer is less than or equal to 3.2 ?m.

Abstract: A low temperature poly-silicon (LTPS) array substrate is disclosed. The array substrate includes a first substrate and a stack structure on the first substrate, where the stack structure includes a first conductive layer, and a second conductive layer. The first and second conductive layers are insulated from each other. The array substrate also includes a polysilicon layer above the first and second conductive layers, an interlayer insulating layer above the polysilicon layer, and a source-drain metal layer on the interlayer insulating layer. The source-drain metal layer includes a source and a drain, the source and the drain are electrically connected with the polysilicon layer through a first via, and one of the source and the drain is electrically connected with the first conductive layer through a second via.

Abstract: A low temperature poly-silicon (LTPS) array substrate is disclosed. The array substrate includes a first substrate and a stack structure on the first substrate, where the stack structure includes a first conductive layer, and a second conductive layer. The first and second conductive layers are insulated from each other. The array substrate also includes a polysilicon layer above the first and second conductive layers, an interlayer insulating layer above the polysilicon layer, and a source-drain metal layer on the interlayer insulating layer. The source-drain metal layer includes a source and a drain, the source and the drain are electrically connected with the polysilicon layer through a first via, and one of the source and the drain is electrically connected with the first conductive layer through a second via.