Abstract: A network buffer memory is divided into pools of locations including a plurality of tinygram contiguous sections and a plurality of jumbogram contiguous sections. The tinygram contiguous sections available for storage of packets are listed in a list of tinygram pointers. The jumbogram contiguous sections available for storage of packets are also listed in a list of jumbogram pointers. A threshold for distinguishing the packets as tinygrams and jumbograms is programmed. As packets are received, they are measured against the threshold. Responsive to detection of an end of packet condition prior to reaching the threshold, storing the packet in a tinygram contiguous section. Otherwise, the packet is stored in a jumbogram contiguous section. Availability of sections is determined by query to the FIFO lists of pointers.

Abstract: A computer system having an improved method of handling interrupts associated with I/O operations to reduce interrupt latencies. The computer system includes one or more processing units, a memory device (e.g., RAM) connected to the processing unit via a system bus, and a plurality of I/O devices providing interrupt sources, connected to the processor via an I/O bus and a bus bridge. The bus bridge has incorporated therein or connected thereto means for intercepting interrupt requests transmitted to the processing unit and handling the interrupt requests without suspending the current process in the processing unit. In the preferred embodiment, the means for intercepting and handling the interrupts includes a storage device or array having pico-code instructions which are scheduled for execution in a sequencer by the interrupt control logic. If the pico-code sees an interrupt that it is not programmed to handle (such as an exception), it can pass that interrupt to the appropriate processing unit for handling.

Abstract: A method and apparatus are provided for processing programmed input/output (PIO) operations in a computer system. A batched list of PIO operations is stored in a buffer. Then the batched list of PIO operations is moved as a single system bus operation to an I/O bus interface unit. The I/O bus interface unit includes sequencer logic. The sequencer logic is used for executing the batched list of PIO operations and for providing an ordered sequence of PIO operations to a system I/O bus. The method and apparatus of the invention enhances the use of non-intelligent I/O adapters in a computer system by reducing the overhead of system PIO operations. Also the correctly ordered sequence of PIO commands provided by the sequencer logic facilitates the use of non-intelligent I/O adapters in reduced instruction-set computer (RISC) systems.

Abstract: A method and apparatus are provided for generation of predicted responses in a computer communications network system. A server in the computer communications network system predicts the client's next request based on the present client's request. The server sets a trigger that recognizes a match of the client's predicted request. When a client's predicted request arrives, the trigger sends the response. Additionally, the server associates a timeout action with the predicted response so that if a predicted request is not received within the timeout interval or other events occur before the predicted request arrives, the triggered response is removed and an alternative action is performed.

Abstract: A method and apparatus processing system for enhancing the processing of a plurality of related packets received at a logical unit within a data processing system are disclosed. A plurality of packets are received at the logical unit. Then each of the plurality of packets are examined and a session identification is obtained for each of the plurality of packets. During a preselected time window, each of the plurality of packets are associated with a group. Each packet in a group has a session identification that is identical to every other packet within the group.