Patents by Inventor Bradley Dobbie

Bradley Dobbie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11119929
    Abstract: Systems and methods of multi-chip processing with low latency and congestion. In a multi-chip processing system, each chip includes a plurality of clusters arranged in a mesh design. A respective interconnect controller is disposed at the end of each column. The column is linked to a corresponding remote column in the other chip. A share cache controller in the column is paired with a corresponding cache controller in the remote column, the pair of cache controllers are configured to control data caching for a same set of main memory locations. Communications between cross-chip cache controllers are performed within linked columns of clusters via the column-specific inter-chip interconnect controllers.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: September 14, 2021
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Craig Barner, David Asher, Richard Kessler, Bradley Dobbie, Daniel Dever, Thomas F. Hummel, Isam Akkawi
  • Patent number: 10599430
    Abstract: Managing instructions on a processor includes: identifying selected instructions as being associated with operations from a stored library of operations. The identifying includes, for instructions included in a particular thread executing on the processor, identifying first/second subsets of the instructions as being associated with a lock/unlock operation based on predetermined characteristics of the instructions. Managing lock/unlock operations associated with the selected instructions that are issued on a first processor core includes, for each instruction included in a first thread and identified as being associated with a lock operation corresponding to a particular lock, in response to determining that the particular lock has already been acquired, continuing to attempt to acquire the particular lock for multiple attempts using a lock operation different from the lock operation in the stored library.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: March 24, 2020
    Assignee: Cavium, LLC
    Inventors: Shubhendu Sekhar Mukherjee, Isam Wadih Akkawi, David Asher, Michael Bertone, David Albert Carlson, Bradley Dobbie, Richard Eugene Kessler
  • Patent number: 10445096
    Abstract: Managing lock and unlock operations for a first thread executing on a first processor core includes, for each instruction included in the first thread and identified as being associated with: (1) a lock operation corresponding to a particular lock, in response to determining that the particular lock has already been acquired, continuing to perform the lock operation for multiple attempts during which the first processor core is not able to execute threads other than the first thread, or (2) an unlock operation corresponding to a particular lock, releasing the particular lock from the first thread. Prioritization of selected messages sent over interconnection circuitry configured to connect each processor core to a memory system of the processor is preserved. The selected messages associated with instructions identified as being associated with an unlock operation are prioritized over messages associated with instructions identified as being associated with a lock operation.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: October 15, 2019
    Assignee: Cavium, LLC
    Inventors: Shubhendu Sekhar Mukherjee, Isam Wadih Akkawi, David Asher, Michael Bertone, David Albert Carlson, Bradley Dobbie, Richard Eugene Kessler
  • Patent number: 10331500
    Abstract: Managing lock and unlock operations for a first thread executing on a first processor core includes, for each instruction included in the first thread and identified as being associated with: (1) a lock operation corresponding to a particular lock stored in a particular memory location, in response to determining that the particular lock has already been acquired, continuing to perform the lock operation for multiple attempts using associated operation messages for accessing the particular memory location, or (2) an unlock operation corresponding to a particular lock stored in a particular memory location, releasing the particular lock from the first thread using an associated operation message for accessing the particular memory location. Selected operation messages associated with an unlock operation are prioritized over operation messages associated with a lock operation.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: June 25, 2019
    Assignee: Cavium, LLC
    Inventors: Shubhendu Sekhar Mukherjee, Isam Wadih Akkawi, David Asher, Michael Bertone, David Albert Carlson, Bradley Dobbie, Richard Eugene Kessler
  • Patent number: 10248420
    Abstract: Managing instructions on a processor includes: executing threads having access to a stored library of operations. For a first thread executing on the first processor core, for each instruction included in the first thread and identified as being associated with a lock operation corresponding to a particular lock, the managing includes determining if the particular lock has already been acquired for another thread executing on a processor core other than the first processor core, and if so, continuing to perform the lock operation for multiple attempts using a hardware lock operation different from the lock operation in the stored library, and if not, acquiring the particular lock for the first thread. The hardware lock operation performs a modified atomic operation that changes a result of the hardware lock operation for failed attempts to acquire the particular lock relative to a result of the lock operation in the stored library.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: April 2, 2019
    Assignee: Cavium, LLC
    Inventors: Shubhendu Sekhar Mukherjee, Isam Wadih Akkawi, David Asher, Michael Bertone, David Albert Carlson, Bradley Dobbie, Richard Eugene Kessler
  • Publication number: 20180293114
    Abstract: Managing lock and unlock operations for a first thread executing on a first processor core includes, for each instruction included in the first thread and identified as being associated with: (1) a lock operation corresponding to a particular lock stored in a particular memory location, in response to determining that the particular lock has already been acquired, continuing to perform the lock operation for multiple attempts using associated operation messages for accessing the particular memory location, or (2) an unlock operation corresponding to a particular lock stored in a particular memory location, releasing the particular lock from the first thread using an associated operation message for accessing the particular memory location. Selected operation messages associated with an unlock operation are prioritized over operation messages associated with a lock operation.
    Type: Application
    Filed: September 7, 2017
    Publication date: October 11, 2018
    Inventors: Shubhendu Sekhar Mukherjee, Isam Wadih Akkawi, David Asher, Michael Bertone, David Albert Carlson, Bradley Dobbie, Richard Eugene Kessler
  • Publication number: 20180293100
    Abstract: Managing lock and unlock operations for a first thread executing on a first processor core includes, for each instruction included in the first thread and identified as being associated with: (1) a lock operation corresponding to a particular lock, in response to determining that the particular lock has already been acquired, continuing to perform the lock operation for multiple attempts during which the first processor core is not able to execute threads other than the first thread, or (2) an unlock operation corresponding to a particular lock, releasing the particular lock from the first thread. Prioritization of selected messages sent over interconnection circuitry configured to connect each processor core to a memory system of the processor is preserved. The selected messages associated with instructions identified as being associated with an unlock operation are prioritized over messages associated with instructions identified as being associated with a lock operation.
    Type: Application
    Filed: May 31, 2017
    Publication date: October 11, 2018
    Inventors: Shubhendu Sekhar Mukherjee, Isam Wadih Akkawi, David Asher, Michael Bertone, David Albert Carlson, Bradley Dobbie, Richard Eugene Kessler
  • Publication number: 20180293113
    Abstract: Managing instructions on a processor includes: executing threads having access to a stored library of operations. For a first thread executing on the first processor core, for each instruction included in the first thread and identified as being associated with a lock operation corresponding to a particular lock, the managing includes determining if the particular lock has already been acquired for another thread executing on a processor core other than the first processor core, and if so, continuing to perform the lock operation for multiple attempts using a hardware lock operation different from the lock operation in the stored library, and if not, acquiring the particular lock for the first thread. The hardware lock operation performs a modified atomic operation that changes a result of the hardware lock operation for failed attempts to acquire the particular lock relative to a result of the lock operation in the stored library.
    Type: Application
    Filed: May 31, 2017
    Publication date: October 11, 2018
    Inventors: Shubhendu Sekhar Mukherjee, Isam Wadih Akkawi, David Asher, Michael Bertone, David Albert Carlson, Bradley Dobbie, Richard Eugene Kessler
  • Publication number: 20180293070
    Abstract: Managing instructions on a processor includes: identifying selected instructions as being associated with operations from a stored library of operations. The identifying includes, for instructions included in a particular thread executing on the processor, identifying first/second subsets of the instructions as being associated with a lock/unlock operation based on predetermined characteristics of the instructions. Managing lock/unlock operations associated with the selected instructions that are issued on a first processor core includes, for each instruction included in a first thread and identified as being associated with a lock operation corresponding to a particular lock, in response to determining that the particular lock has already been acquired, continuing to attempt to acquire the particular lock for multiple attempts using a lock operation different from the lock operation in the stored library.
    Type: Application
    Filed: May 31, 2017
    Publication date: October 11, 2018
    Inventors: Shubhendu Sekhar Mukherjee, Isam Wadih Akkawi, David Asher, Michael Bertone, David Albert Carlson, Bradley Dobbie, Richard Eugene Kessler
  • Patent number: 9870328
    Abstract: Communicating among multiple sets of multiples cores includes: buffering messages in first buffer associated with a first set of multiple cores; buffering messages in a second buffer associated with a second set of multiple cores; and transferring messages over communication circuitry from cores not in the first set to the first buffer, and to transferring messages from cores not in the second set to the second buffer. A first core of the first set sends messages corresponding to multiple types of instructions to a second core of the second set through the communication circuitry. The second buffer is large enough to store a maximum number of instructions of a second type that are allowed to be outstanding from cores in the first set at the same time, and still have enough storage space for one or more instructions of a first type.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: January 16, 2018
    Assignee: CAVIUM, INC.
    Inventors: Shubhendu Sekhar Mukherjee, David Asher, Bradley Dobbie, Thomas Hummel, Daniel Dever
  • Patent number: 9665505
    Abstract: A motherboard includes multiple sockets, each socket configured to accept an integrated circuit. A first integrated circuit in a first socket includes one or more cores and at least one buffer. A second integrated circuit in a second socket includes one or more cores and at least one buffer. Communication circuitry transfers messages to buffers of integrated circuits coupled to different sockets. A first core on the first integrated circuit is configured to send messages corresponding to multiple types of instructions to a second core on the second integrated circuit through the communication circuitry. The buffer of the second integrated circuit is large enough to store a maximum number of instructions of a second type that are allowed to be outstanding from cores on the first integrated circuit at the same time, and still have enough storage space for one or more instructions of a first type.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: May 30, 2017
    Assignee: CAVIUM, INC.
    Inventors: Shubhendu Sekhar Mukherjee, David Asher, Bradley Dobbie, Thomas Hummel, Daniel Dever
  • Patent number: 9501425
    Abstract: Each of multiple translation lookaside buffers (TLBs) is associated with a corresponding processing element. A first TLB invalidation (TLBI) instruction is issued at a first processing element, and sent to a second processing element. An element-specific synchronization instruction is issued at the first processing element. A synchronization command is broadcast, and received at the second processing element. The element-specific synchronization instruction prevents issuance of additional TLBI instructions at the first processing element until an acknowledgement in response to the synchronization command is received at the first processing element.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: November 22, 2016
    Assignee: Cavium, Inc.
    Inventors: Shubhendu S. Mukherjee, David Asher, Mike Bertone, Bradley Dobbie, Thomas Hummel