Abstract: According to the present disclosure, devices, systems, and methods for locating, tracking, and conducting communications between care devices and networks of care facilities through local communications hubs.

Abstract: A method for removing material from a rock wall. The method includes moving a cutting edge through the rock wall to create a first slot in the rock wall, moving the cutting edge through the rock wall to create a second slot in the rock wall, the second slot being separated from the first slot by an uncut portion, the uncut portion defining a base surface attached to the wall, cutting a notch into the base surface of the uncut portion, and applying a force on the uncut portion to break the uncut portion away from the wall.

Abstract: Example apparatus and methods related to automated diagnostic analyzers having rear accessible track systems are described herein. An example apparatus disclosed herein includes an analyzer to perform a diagnostic test. The analyzer has a first side and a second side opposite the first side. The example apparatus includes a loading bay disposed on the first side of the analyzer to receive a first carrier and a pipetting mechanism coupled to the analyzer adjacent the second side. The example apparatus also includes a first carrier shuttle to transport the first carrier from a first location adjacent the loading bay to a second location adjacent the pipetting mechanism and a track disposed adjacent the second side of the analyzer to transfer a second carrier to a third location adjacent the pipetting mechanism.

Abstract: Example apparatus and methods related to automated diagnostic analyzers having rear accessible track systems are described herein. An example apparatus disclosed herein includes an analyzer to perform a diagnostic test. The analyzer has a first side and a second side opposite the first side. The example apparatus includes a loading bay disposed on the first side of the analyzer to receive a first carrier and a pipetting mechanism coupled to the analyzer adjacent the second side. The example apparatus also includes a first carrier shuttle to transport the first carrier from a first location adjacent the loading bay to a second location adjacent the pipetting mechanism and a track disposed adjacent the second side of the analyzer to transfer a second carrier to a third location adjacent the pipetting mechanism.

Abstract: Example apparatus and methods related to automated diagnostic analyzers having rear accessible track systems are described herein. An example apparatus disclosed herein includes an analyzer to perform a diagnostic test. The analyzer has a first side and a second side opposite the first side. The example apparatus includes a loading bay disposed on the first side of the analyzer to receive a first carrier and a pipetting mechanism coupled to the analyzer adjacent the second side. The example apparatus also includes a first carrier shuttle to transport the first carrier from a first location adjacent the loading bay to a second location adjacent the pipetting mechanism and a track disposed adjacent the second side of the analyzer to transfer a second carrier to a third location adjacent the pipetting mechanism.

Abstract: Example apparatus and methods related to automated diagnostic analyzers having rear accessible track systems. An example apparatus disclosed herein includes an analyzer to perform a diagnostic test, the analyzer having a first side and a second side opposite the first side. The example apparatus includes a loading bay disposed on the first side of the analyzer to receive a first carrier and a pipetting mechanism coupled to the analyzer adjacent the second side. The example apparatus also includes a first carrier shuttle to transport the first carrier from a first location adjacent the loading bay to a second location adjacent the pipetting mechanism and a track disposed adjacent the second side of the analyzer to transfer a second carrier to a third location adjacent the pipetting mechanism.

Abstract: Example apparatus and methods related to automated diagnostic analyzers having rear accessible track systems. An example apparatus disclosed herein includes an analyzer to perform a diagnostic test, the analyzer having a first side and a second side opposite the first side. The example apparatus includes a loading bay disposed on the first side of the analyzer to receive a first carrier and a pipetting mechanism coupled to the analyzer adjacent the second side. The example apparatus also includes a first carrier shuttle to transport the first carrier from a first location adjacent the loading bay to a second location adjacent the pipetting mechanism and a track disposed adjacent the second side of the analyzer to transfer a second carrier to a third location adjacent the pipetting mechanism.

Abstract: Example apparatus and methods related to automated diagnostic analyzers having rear accessible track systems. An example apparatus disclosed herein includes an analyzer to perform a diagnostic test, the analyzer having a first side and a second side opposite the first side. The example apparatus includes a loading bay disposed on the first side of the analyzer to receive a first carrier and a pipetting mechanism coupled to the analyzer adjacent the second side. The example apparatus also includes a first carrier shuttle to transport the first carrier from a first location adjacent the loading bay to a second location adjacent the pipetting mechanism and a track disposed adjacent the second side of the analyzer to transfer a second carrier to a third location adjacent the pipetting mechanism.

Abstract: An electronic device can include electronic components and an insulating layer overlying the electronic components. The electronic device can also include a capacitor overlying the insulating layer, wherein the capacitor includes a first electrode and a second electrode. The second electrode can include an opening, wherein from a top view, a defect lies within the opening. In another aspect, a process of forming an electronic device can include forming a first capacitor electrode layer over a substrate, forming a dielectric layer over the first capacitor electrode layer, and forming a second capacitor electrode layer over the dielectric layer. The process can also include detecting a defect and removing a first portion of the second capacitor electrode layer corresponding to the defect, wherein a second portion of the second capacitor electrode layer remains over the dielectric layer.

Abstract: A mechanism is provided for extending useable lifetimes of semiconductor devices that are subject to trapped charge carriers in a gate dielectric. Embodiments of the present invention provide heat to the gate dielectric region from one or more sources, where the heat sources are included in a package along with the semiconductor device. It has been determined that heat, when applied during a period when the channel region of a transistor is in accumulation mode or is not providing a current across the channel, can at least partially recover the device from trapped charge carrier effects. Embodiments of the present invention supply heat to the affected gate dielectric region using mechanisms available where the semiconductor device is used (e.g., in the field).

Abstract: A mechanism is provided for extending useable lifetimes of semiconductor devices that are subject to trapped charge carriers in a gate dielectric. Embodiments of the present invention provide heat to the gate dielectric region from one or more sources, where the heat sources are included in a package along with the semiconductor device. It has been determined that heat, when applied during a period when the channel region of a transistor is in accumulation mode or is not providing a current across the channel, can at least partially recover the device from trapped charge carrier effects. Embodiments of the present invention supply heat to the affected gate dielectric region using mechanisms available where the semiconductor device is used (e.g., in the field).

Abstract: Example apparatus and methods related to automated diagnostic analyzers having rear accessible track systems. An example apparatus disclosed herein includes an analyzer to perform a diagnostic test, the analyzer having a first side and a second side opposite the first side. The example apparatus includes a loading bay disposed on the first side of the analyzer to receive a first carrier and a pipetting mechanism coupled to the analyzer adjacent the second side. The example apparatus also includes a first carrier shuttle to transport the first carrier from a first location adjacent the loading bay to a second location adjacent the pipetting mechanism and a track disposed adjacent the second side of the analyzer to transfer a second carrier to a third location adjacent the pipetting mechanism.

Abstract: A first dielectric layer is formed on a substrate in a transistor region and an NVM region, a first conductive layer is formed on the first dielectric layer, a second dielectric layer is formed on the first conductive layer, and a second conductive layer is formed over the second dielectric layer. A patterned etch is performed to remove at least a portion of the second conductive layer in the transistor region and to expose an extension portion of the first conductive layer. A first mask is formed over the transistor region having a first pattern, wherein the first pattern is of a gate stack of the MOSFET and an extension in the extension portion extending from the gate stack, and a second mask over the NVM region having a second pattern, wherein the second pattern is of a gate stack of the NVM cell. A patterned etch is then performed.

Abstract: A gate-edge diode is made in a diode region of a substrate and a non-volatile memory cell is made in an NVM region of the substrate. A first dielectric layer is formed on the substrate in the diode region and the NVM region. A first conductive layer is formed on the first dielectric layer. A second dielectric layer is formed on the first conductive layer. A second conductive layer is formed over the second dielectric layer. A first mask is formed over the diode region having a first pattern. The first pattern is of a plurality of fingers and a second mask over the NVM region has a second pattern. The second pattern is of a gate stack of the non-volatile memory cell. An etch is performed through the second conductive layer, the second dielectric layer, and the first conductive layer to leave the first pattern of the plurality of fingers in the diode region and the second pattern of the gate stack in the NVM region.

Abstract: A capacitor and an NVM cell are formed in an integrated fashion so that the etching of the capacitor is useful in end point detection of an etch of the NVM cell. This is achieved using two conductive layers over an NVM region and over a capacitor region. The first conductive layer is patterned in preparation for a subsequent patterning step which includes a step of patterning both the first conductive layer and the second conductive layer in both the NVM region and the capacitor region. The subsequent etch provides for an important alignment of a floating gate to the overlying control gate by having both conductive layers etched using the same mask. During this subsequent etch, the fact that first conductive material is being etched in the capacitor region helps end point detection of the etch of the first conductive layer in the NVM region.

Abstract: A gate-edge diode is made in a diode region of a substrate and a non-volatile memory cell is made in an NVM region of the substrate. A first dielectric layer is formed on the substrate in the diode region and the NVM region. A first conductive layer is formed on the first dielectric layer. A second dielectric layer is formed on the first conductive layer. A second conductive layer is formed over the second dielectric layer. A first mask is formed over the diode region having a first pattern. The first pattern is of a plurality of fingers and a second mask over the NVM region has a second pattern. The second pattern is of a gate stack of the non-volatile memory cell. An etch is performed through the second conductive layer, the second dielectric layer, and the first conductive layer to leave the first pattern of the plurality of fingers in the diode region and the second pattern of the gate stack in the NVM region.

Abstract: A first dielectric layer is formed on a substrate in a transistor region and an NVM region, a first conductive layer is formed on the first dielectric layer, a second dielectric layer is formed on the first conductive layer, and a second conductive layer is formed over the second dielectric layer. A patterned etch is performed to remove at least a portion of the second conductive layer in the transistor region and to expose an extension portion of the first conductive layer. A first mask is formed over the transistor region having a first pattern, wherein the first pattern is of a gate stack of the MOSFET and an extension in the extension portion extending from the gate stack, and a second mask over the NVM region having a second pattern, wherein the second pattern is of a gate stack of the NVM cell. A patterned etch is then performed.

Abstract: A capacitor and an NVM cell are formed in an integrated fashion so that the etching of the capacitor is useful in end point detection of an etch of the NVM cell. This is achieved using two conductive layers over an NVM region and over a capacitor region. The first conductive layer is patterned in preparation for a subsequent patterning step which includes a step of patterning both the first conductive layer and the second conductive layer in both the NVM region and the capacitor region. The subsequent etch provides for an important alignment of a floating gate to the overlying control gate by having both conductive layers etched using the same mask. During this subsequent etch, the fact that first conductive material is being etched in the capacitor region helps end point detection of the etch of the first conductive layer in the NVM region.

Abstract: In one embodiment, a method of forming a via includes providing a semiconductor substrate, wherein the semiconductor substrate comprises a through-via region, forming isolation openings and a sacrificial feature in the through-via region, filling the isolation openings to form isolation regions, forming a dielectric layer over the semiconductor substrate after filling the isolation openings, forming a first portion of a through-via opening in the dielectric layer, forming a second portion of the through-via opening in the semiconductor substrate, wherein forming the second portion of the through-via opening comprises removing the sacrificial feature, and forming a conductive material in the first portion and the second portion of the through-via opening.